Paul Molitor, Janett Mohnke

Equivalence Checking of Digital Circuits (eBook, PDF)

Fundamentals, Principles, Methods

• Format: PDF

Produktbeschreibung

Hardware veri?cation is the process of checking whether a design conforms to its speci?cations of functionality and timing. In today's design processes it becomes more and more important. Very large scale integrated (VLSI) circuits and the resulting digital systems have conquered a place in almost all areas of our life, even in security sensitive applications. Complex digital systems control airplanes, have been used in banks and on intensive-care units. Hence, the demand for error-free designs is more important than ever. In addition, economic reasons underline this demand as well. The design and production process of present day VLSI-circuits is highly time- and cost-intensive. Mo- over, it is nearly impossible to repair integrated circuits. Thus, it is desirable to detect design errors early in the design process and not just after producing the prototype chip. All these facts are re?ected by developing and prod- tion statistics of present day companies. For example, In?neon Technologies [118] assumed that about 60% to 80% of the overall design time was spent for veri?cation in 2000. Other sources cite the 3-to-1 head count ratio between veri?cation engineers and logic designers. This shows that verifying logical correctness of the design of hardware systems is a major gate to the problem of time-to-market (cf. [113]). With the chip complexity constantly increasing, the dif?culty as well as the - portance of functional veri?cation of new product designs has been increased. It is not only more important to get error-free designs.

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Produktdetails

• Verlag: Springer New York
• Seitenzahl: 263
• Erscheinungstermin: 8. Mai 2007
• Englisch
• ISBN-13: 9781402026034
• Artikelnr.: 44001074

Autorenporträt

Paul Molitor ist Professor für Technische Informatik an der Martin-Luther-Universität Halle-Wittenberg. Vor seiner Tätigkeit an der Universität Halle war er Professor für Schaltungstechnik an der Humboldt-Universität zu Berlin (1993/94) bzw. Projektleiter in dem an der Universität des Saarlandes und der Universität Kaiserslautern angegliederten Sonderforschungsbereich 'VLSI Entwurfsmethoden und Parallelität' (1983-92). Er studierte Informatik und Mathematik an der Universität des Saarlandes (Diplom 1982, Promotion 1986, Habilitation 1992).

Inhaltsangabe

Fundamentals.- Preliminaries.- Representation of Boolean and Pseudo Boolean Functions.- Equivalence Checking of Combinational Circuits.- Use of Canonical Data Structures.- SAT and ATPG Based Equivalence Checking.- Exploiting Similarities.- Checking Equivalence for Partial Implementations.- Permutation Independent Boolean Comparison.- Equivalence Checking of Sequential Circuits.- Formal Basics.- The Latch Correspondence Problem.