Michael Pecht, Riko Radojcic, Gopal Rao

Guidebook for Managing Silicon Chip Reliability

• Broschiertes Buch

Produktbeschreibung

Achieving cost-effective performance over time requires an organized, disciplined, and time-phased approach to product design, development, qualification, manufacture, and in-service management. This book examines the principal failure mechanisms associated with modern integrated circuits and describes common practices used to resolve them. It provides a framework for how to model the mechanism, test for defects, and avoid and manage damage. The authors focus on device failure and causes, outlines how to establish the specifications defining chip performance, cost, quality, and reliability, and they include an extensive table detailing the types of mechanism failures.

Produktdetails

• Verlag: Taylor & Francis Ltd (Sales)
• Seitenzahl: 224
• Erscheinungstermin: 7. Oktober 2019
• Englisch
• Abmessung: 234mm x 156mm x 12mm
• Gewicht: 322g
• ISBN-13: 9780367400064
• ISBN-10: 0367400065
• Artikelnr.: 58053000

Autorenporträt

Pecht, Michael; Radojcic, Riko; Rao, Gopal

Inhaltsangabe

Introduction How Devices Fail Intrinsic Mechanisms Extrinsic Mechanisms
Intrinsic Device Sensitivities Device Transconductance Sensitivities
Leakage Current Sensitivities Breakdown Issues Electromigration Description
of the Mechanism Modeling of the Mechanism How to Detect/Test How to Manage
Hot Carrier Aging Description of the Mechanism Modeling of the Mechanism
Detection of Hot Carrier Aging Avoidance of Hot Carrier Aging Time
Dependent Dielectric Breakdown Description of the Mechanism Modeling of the
Mechanism How to Detect/Test How to Avoid and Manage Mechanical Stress
Induced Migration Description of the Mechanism Modeling of the Mechanism
How to Detect/Test How to Manage Alpha Particle Sensitivity Description of
the Mechanism Modeling of the Mechanism Prevention of Alpha Particle
Induced Damage Electrostatic Discharge and Electrical Overstress
Description of the Mechanism Modeling of the Mechanism Avoiding ESD/EOS
Failures Latch-Up Description of the Mechanism How to Detect How to Avoid
Qualification Qualification Testing Virtual Qualification Screening
Functional Tests Burn-In Tests Iddq Tests Design for Reliability Design
System Effective Management of Wear-Out Failures Extrinsic Reliability
Mechanisms Infant Mortality Failure Mechanisms Circuit Sensitivities
Summary