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New nanometric technologies hold the promise of device integration density increases of several orders of magnitude and, accordingly, an increase of system performance and functionality. However, this improved integration density comes at the cost of a dramatic reduction of several orders of magnitude on the device quality and, in general, on the operation reliability of circuits. The causes for this increased error rate are inherent to the device's dimensions. It is widely acknowledged that fault and defect tolerant strategies will be required in future nanoelectronic systems. This book analyzes the aggression sources causing the increased fault rates and how they affect the reliability of logic gate operation. From this analysis a new logic cell structure is designed and analyzed. The cell is proposed to be used as the building block for a hierarchical approach to fault-tolerant nanoelectronic architectures. This book will be especially useful for researchers and engineers working in the development of nanoelectronic systems.