A Novel approach for Fault Tolerant Nano Memory Applications - Pavan Kumar, Chinnala
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NANOTECHNOLOGY provides smaller, faster, and lower energy devices which allow more powerful and compact circuitry; However, these benefits come with a cost-the nanoscale devices may be less reliable. Thermal- and shot-noise estimations alone suggest that the transient fault rate of an individual nanoscale device (e.g., transistor or nanowire) may be orders of magnitude higher than today's devices. A failure is said to have occurred in a circuit or system if it deviates from its specified behavior. A fault on the other hand is physical defect which may or may not cause a failure. The failure…mehr

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Produktbeschreibung
NANOTECHNOLOGY provides smaller, faster, and lower energy devices which allow more powerful and compact circuitry; However, these benefits come with a cost-the nanoscale devices may be less reliable. Thermal- and shot-noise estimations alone suggest that the transient fault rate of an individual nanoscale device (e.g., transistor or nanowire) may be orders of magnitude higher than today's devices. A failure is said to have occurred in a circuit or system if it deviates from its specified behavior. A fault on the other hand is physical defect which may or may not cause a failure. The failure rate, also known as the hazard rate and defined as number of failures per unit time compared with the number of surviving components. A fault is characterized by its nature, value, extent & duration.
Autorenporträt
Ch. Pavan Kumar has completed B.Tech and M.Tech from JNTUH and pursuing Ph.D from JNTUH, India, Presently working as Asst Prof in KITS Warangal. Dr.K.Sivani completed B.Tech from KU, Wgl and M.Tech from NIT Wgl India then PhD from JNTU, Hyderabad, India. Presently working as Professor in KITS wgl. Interesting fields are VLSI and Signal Processing.