Andere Kunden interessierten sich auch für
![Defect and Fault Tolerance in VLSI Systems]( "Defect and Fault Tolerance in VLSI Systems")
Defect and Fault Tolerance in VLSI Systems110,99 €![Defects in HIgh-k Gate Dielectric Stacks]( "Defects in HIgh-k Gate Dielectric Stacks")
Defects in HIgh-k Gate Dielectric Stacks154,99 €![Sub-Threshold Design for Ultra Low-Power Systems]( "Sub-Threshold Design for Ultra Low-Power Systems")
Sub-Threshold Design for Ultra Low-Power Systems183,99 €![Sub-threshold Design for Ultra Low-Power Systems]( "Sub-threshold Design for Ultra Low-Power Systems")
Sub-threshold Design for Ultra Low-Power Systems110,99 €![Embedded Memories for Nano-Scale VLSIs]( "Embedded Memories for Nano-Scale VLSIs")
Embedded Memories for Nano-Scale VLSIs110,99 €![Design for Manufacturability and Yield for Nano-Scale CMOS]( "Design for Manufacturability and Yield for Nano-Scale CMOS")
Design for Manufacturability and Yield for Nano-Scale CMOS74,99 €![Design for Manufacturability and Yield for Nano-Scale CMOS]( "Design for Manufacturability and Yield for Nano-Scale CMOS")
Design for Manufacturability and Yield for Nano-Scale CMOS74,99 €
Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditionsand with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.