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Heterogeneous multiprocessor systems-on-chip (MPSoCs) are key components of modern electronic systems. Future MPSoCs feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). Data is transmitted between system cores using high-speed serial links within a packet based network-on-chip (NoC). In this work concepts and circuits for local clock generation in heterogeneous GALS MPSoCs are developed with special focus on the clocking demands of power management and NoC. The clock generators are to be instantiated individually per processor core. For this purpose ultra compact all digital phaselocked loop (ADPLL) frequency synthesizers are developed that provide low jitter clocks, allow fast lock-in and enable instantaneous changes of the output clock frequency. The circuits are implemented in 65nm and 28nm CMOS technologies.