Automating Dummy Fill for DSM Technology
A Deep Learning Approach
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Rising complexity of VLSI designs & IC process technologies increases mismatch between design and manufacturing. The resemblance between a circuit fabricated on the wafer and as designed in the layout tool grows weaker. Process variations, fabrication defects, etc. form new cost (turnaround time, productivity) bottlenecks as we enter the era of nanometer-scale VLSI. This motivates research to enhance the predictability and yield of VLSI manufacturing, as well as design technology means of overcoming process variations and lithographic errors. A CMP and other manufacturing steps in deep submicr...
Rising complexity of VLSI designs & IC process technologies increases mismatch between design and manufacturing. The resemblance between a circuit fabricated on the wafer and as designed in the layout tool grows weaker. Process variations, fabrication defects, etc. form new cost (turnaround time, productivity) bottlenecks as we enter the era of nanometer-scale VLSI. This motivates research to enhance the predictability and yield of VLSI manufacturing, as well as design technology means of overcoming process variations and lithographic errors. A CMP and other manufacturing steps in deep submicron VLSI have varying effects on the device and interconnect features, depending on local characteristics of the layout. To improve manufacturability and performance predictability & to make a layout uniform with respect to prescribed density criteria, insertion of "dummy fill" geometries into the layout is done. Full chip dummy fill is an iterative process,time-consuming and increases the size of GDS. In this book, a more sophisticated dummy-fill insertion algorithm that optimizes the use of metal fill features to satisfy fill requirements, depending on the needs of design is discussed.
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