• Produktbild: Algorithm-Architecture Matching for Signal and Image Processing
  • Produktbild: Algorithm-Architecture Matching for Signal and Image Processing
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Algorithm-Architecture Matching for Signal and Image Processing Best papers from Design and Architectures for Signal and Image Processing 2007 & 2008 & 2009

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Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

01.12.2012

Herausgeber

Guy Gogniat + weitere

Verlag

Springer Netherland

Seitenzahl

296

Maße (L/B/H)

23,5/15,5/1,7 cm

Gewicht

470 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-94-007-3392-3

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

01.12.2012

Herausgeber

Verlag

Springer Netherland

Seitenzahl

296

Maße (L/B/H)

23,5/15,5/1,7 cm

Gewicht

470 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-94-007-3392-3

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: GPSR Kontakt

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  • Produktbild: Algorithm-Architecture Matching for Signal and Image Processing
  • Produktbild: Algorithm-Architecture Matching for Signal and Image Processing
  • Preface. Part 1: Architectures for embedded applications. Chapter 1: Architectures for image processing. Lossless Multi-mode Interband Image Compression and its Hardware Architecture. Efficient Memory Management for Uniform and Recursive Grid Traversal. Chapter 2: Architectures for signal and telecommunication processing. Mapping a Telecommunication Application on a Multiprocessor System-on-Chip. Part 2: Data acquisition and embedded systems. Chapter 3: Sensors for data acquisition. A Standard 3.5T CMOS Imager including a Light Adaptive System for Integration Time Optimization. Chapter 4: Operators for embedded systems. Approximate Multiplication and Division for Arithmetic Data Value Speculation in a RISC Processor. Chapter 5: Partial and dynamic reconfiguration for signal and image processing. RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip. A New three-Level Strategy for Off-line Placement of Hardware Tasks on Partially and Dynamically Reconfigurable Hardware. End-to-end Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems. Part 3: Embedded systems design. Chapter 6: RTOS for embedded systems. SystemC multiprocessor RTOS model for services distribution on MPSoC platforms. Chapter 7: Scheduling of embedded systems. A List Scheduling Heuristic with New Node Priorities and Critical Child Technique for Task Scheduling with Communication Contention. Multiprocessor scheduling of dataflow programs within the Reconfigurable Video Coding framework. Chapter 8: CAD tools for signal and image processing. A High Level Synthesis Flow Using Model Driven Engineering. Generation of Hardware/Software systems based on CAL dataflow description.