Katarzyna Radecka, Zeljko Zilic

Verification by Error Modeling (eBook, PDF)

Using Testing Techniques in Hardware Verification

• Format: PDF

Produktbeschreibung

This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

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Produktdetails

• Verlag: Springer New York
• Seitenzahl: 216
• Erscheinungstermin: 17. Dezember 2005
• Englisch
• ISBN-13: 9780306487392
• Artikelnr.: 44047112

Inhaltsangabe

Boolean Function Representations.- Don't Cares and Their Calculation.- Testing.- Design Error Models.- Design Verification by At.- Identifying Redundant Gate and Wire Replacements.- Conclusions and Future Work.

Rezensionen

From the reviews: "This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. ... The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)