Li (Li Yang) Suny

SiP System-in-Package Design and Simulation (eBook, ePUB)

Mentor EE Flow Advanced Design Guide

• Format: ePub

Produktbeschreibung

An advanced reference documenting, in detail, every step of a real System-in-Package (SiP) design flow Written by an engineer at the leading edge of SiP design and implementation, this book demonstrates how to design SiPs using Mentor EE Flow. Key topics covered include wire bonding, die stacks, cavity, flip chip and RDL (redistribution layer), Embedded Passive, RF design, concurrent design, Xtreme design, 3D real-time DRC (design rule checking), and SiP manufacture. Extensively illustrated throughout, System in Package Design and Simulation covers an array of issues of vital concern for SiP design and fabrication electronics engineers, as well as SiP users, including: * Cavity and sacked dies design * FlipChip and RDL design * Routing and coppering * 3D Real-Time DRC check * SiP simulation technology * Mentor SiP Design and Simulation Platform Designed to function equally well as a reference, tutorial, and self-study, System in Package Design and Simulation is an indispensable working resource for every SiP designer, especially those who use Mentor design tools.

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Produktdetails

• Verlag: John Wiley & Sons
• Seitenzahl: 496
• Erscheinungstermin: 14. Juli 2017
• Englisch
• ISBN-13: 9781119046004
• Artikelnr.: 52557578

Autorenporträt

Mr. Suny Li (Li Yang) is a SiP/PCB Technical Specialist in China; he now works in AcconSys Technology Co. Ltd, (a Mentor Authorized Distributor for China). Suny has guided and consulted on dozens of SiP projects in China, accumulating plentiful experience in SiP design and simulation. Suny has 10 years' experience in and knowledge of Application Engineer for Mentor, especially in SiP/PCB design and simulation. Before this, Suny worked in the Chinese Academy of Science and SIEMENS for several years. He has more than seven years' experience in hardware design (HW system design, PCB layout, high-speed signal integrity, power integrity, EMI, etc.). In the course of his work, Suny has published papers and acquired four patents, and he continues with this work. Suny is a senior member of the Chinese Institute of Electronics (CIE) and a member of the IEEE. Suny graduated from Beijing University of Aeronautics & Astronautics (BUAA) in 2000, receiving Master's and Bachelor's degrees in Science and Technology of Aeronautics & Astronautics.

Inhaltsangabe

About the author xiii

Preface xv

1 SiP Design and Simulation Platform 1

1.1 From Package to SiP 1

1.2 The Development of Mentor SiP Design Technology 5

1.3 The Mentor SiP Design and Simulation Platform 6

1.3.1 SiP Platform Introduction 6

1.3.2 Schematic Input 8

1.3.3 Concurrent System Design 8

1.3.4 SiP Board Design 9

1.3.5 Signal Integrity and Power Integrity Simulation 13

1.3.6 Thermal Analysis 13

1.3.7 The Advantages of the Mentor SiP Design and Simulation Platform 14

1.4 The Introduction of the Finished Project 16

2 Introduction to Package 19

2.1 Definition and Function of Package 19

2.2 Development of Packaging Technology 20

2.3 SiP and Related Technologies 24

2.3.1 The Appearance of SiP Technology 24

2.3.2 SoC and SiP 25

2.3.3 SiP?]Related Technologies 26

2.4 The Development of the Package Market 31

2.5 Package Manufacturers 32

2.5.1 Traditional Package Manufacturers 32

2.5.2 New SiP Manufacturers in Different Areas 34

2.6 Bare Chip Suppliers 35

3 The SiP Production Process 37

3.1 BGA: The Mainstream SiP Package Form 37

3.2 The SiP Package Production Process 39

3.3 Three Key Elements of SiP 41

4 New Package Technologies 45

4.1 TSV (Through Silicon Via) Technology 45

4.1.1 TSV Introduction 45

4.1.2 TSV Technical Characteristics 46

4.1.3 TSV Application and Prospects 48

4.2 Integrated Passive Device (IPD) Technology 49

4.2.1 IPD Introduction 49

4.2.2 The Advantages of IPD 50

4.3 Package on Package (PoP) Technology 51

4.3.1 The Limitations of 3D SiP 51

4.3.2 The Application of PoP 52

4.3.3 The Emphasis in PoP Design 54

4.4 Apple A8 processor - an Example of a PoP Product 55

5 SiP Design and Simulation Flow 59

5.1 SiP Design and Simulation Flow 59

5.2 Design and Simulation Process in Mentor EE Flow 61

5.2.1 Library Creation 61

5.2.2 Schematic Design 62

5.2.3 Layout Design 63

5.2.4 Design Simulation 66

6 Central Library 67

6.1 The Structure of the Central Library 67

6.2 Introduction to the Dashboard 68

6.3 Schematic Symbol Creation 70

6.4 Bare Chip Cell Creation 76

6.4.1 Create Bare Chip Padstack 76

6.4.2 Create Bare Chip Cell 78

6.5 BGA Cell Creation 82

6.5.1 Create BGA Padstack 82

6.5.2 Create BGA Cell Manually 84

6.5.3 Create BGA Cell with Die Wizard 88

6.5.4 LP Wizard Professional Library Tool 89

6.6 Part Creation 90

6.7 Create Cell Via Part 92

7 Schematic Input 97

7.1 Netlist Input 97

7.2 Basic Schematic Input 99

7.2.1 Start DxDesigner 99

7.2.2 Create New Project 105

7.2.3 Schematic Design Check 110

7.2.4 Design Rules Setup 110

7.2.5 Package Design 112

7.2.6 Partlist Output 115

7.2.7 Chinese Input in Schematic 117

7.2.8 Enter Layout Environment 118

7.3 Schematic Input Based on DxDataBook 120

7.3.1 DxDataBook Introduction 120

7.3.2 DxDataBook Usage 121

7.3.3 Check and Update Component Properties 123

8 Multi-board Project Management and Concurrent Schematic Design 127

8.1 Multi-Board Project Management 127

8.1.1 SiP and PCB Collaborative Design 127

8.1.2 Multi-Board Project Des