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This book is the first to explain FinFET modeling for IC simulation and the industry standard - BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture, as now enabled by the approved industry standard.
The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, providing a step-by-step approach for the efficient extraction of model parameters.
With this book you
…mehr

Produktbeschreibung
This book is the first to explain FinFET modeling for IC simulation and the industry standard - BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture, as now enabled by the approved industry standard.

The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, providing a step-by-step approach for the efficient extraction of model parameters.

With this book you will learn:

  • Why you should use FinFET
  • The physics and operation of FinFET
  • Details of the FinFET standard model (BSIM-CMG)
  • Parameter extraction in BSIM-CMG
  • FinFET circuit design and simulation
  • Authored by the lead inventor and developer of FinFET, and developers of the BSIM-CM standard model, providing an experts' insight into the specifications of the standard
  • The first book on the industry-standard FinFET model - BSIM-CMG

Dieser Download kann aus rechtlichen Gründen nur mit Rechnungsadresse in A, B, BG, CY, CZ, D, DK, EW, E, FIN, F, GR, HR, H, IRL, I, LT, L, LR, M, NL, PL, P, R, S, SLO, SK ausgeliefert werden.

Autorenporträt
Yogesh S. Chauhan is an assistant professor in EE department at Indian Institute of Technology Kanpur, India. He received Ph.D. degree in compact modeling of high voltage MOSFETs in 2007 from EPFL Switzerland. During 2007-2010, he was manager in IBM Bangalore where he led compact modeling team focusing on RF bulk and SOI transistors and ESD modeling team. During 2010-2012, he was postdoctoral fellow at University of California Berkeley, where he worked on development of bulk and multigate transistor models including BSIM6, BSIM-IMG and BSIM-CMG. He received IBM faculty award in 2013 for his contribution in compact modeling. He has co-authored over 50 conference and journal publications in the field of device compact modeling.