
Vertical 3D Memory Technologie
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The large scale integration and planar scaling of individualsystem chips is reaching an expensive limit. If individual chipsnow, and later terrabyte memory blocks, memory macros, andprocessing cores, can be tightly linked in optimally designed andprocessed small footprint vertical stacks, then performance can beincreased, power reduced and cost contained. This book reviews forthe electronics industry engineer, professional and student thecritical areas of development for 3D vertical memory chipsincluding: gate-all-around and junction-less nanowire memories,stacked thin film and double gate mem...
The large scale integration and planar scaling of individualsystem chips is reaching an expensive limit. If individual chipsnow, and later terrabyte memory blocks, memory macros, andprocessing cores, can be tightly linked in optimally designed andprocessed small footprint vertical stacks, then performance can beincreased, power reduced and cost contained. This book reviews forthe electronics industry engineer, professional and student thecritical areas of development for 3D vertical memory chipsincluding: gate-all-around and junction-less nanowire memories,stacked thin film and double gate memories, terrabit verticalchannel and vertical gate stacked NAND flash, large scale stackingof Resistance RAM cross-point arrays, and 2.5D/3D stacking ofmemory and processor chips with through-silicon-via connections now and remote links later.
Key features:
Presents a review of the status and trends in 3-dimensionalvertical memory chip technologies.
Extensively reviews advanced vertical memory chip technologyand development
Explores technology process routes and 3D chip integration in asingle reference
Key features:
Presents a review of the status and trends in 3-dimensionalvertical memory chip technologies.
Extensively reviews advanced vertical memory chip technologyand development
Explores technology process routes and 3D chip integration in asingle reference