The Designer's Guide to Jitter in Ring Oscillators - McNeill, John A.;Ricketts, David
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This is a book for engineers concerned with jitter: the e ects of noise visible in the time domain. The material presented will be helpful for work at both the system level and the circuit level: At the system level, the challenge is to describe, specify, and measure time domain uncertainty and when necessary, relate jitter to phase noise speci cations in the frequency domain. At the circuit level, the challenge is to design low noise circuitry within power, area, and process constraints so that ultimate performance meets system level requirements. Throughout the book concepts are presented in…mehr

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Produktbeschreibung
This is a book for engineers concerned with jitter: the e ects of noise visible in the time domain. The material presented will be helpful for work at both the system level and the circuit level: At the system level, the challenge is to describe, specify, and measure time domain uncertainty and when necessary, relate jitter to phase noise speci cations in the frequency domain. At the circuit level, the challenge is to design low noise circuitry within power, area, and process constraints so that ultimate performance meets system level requirements. Throughout the book concepts are presented in the context of an - gineering application requiring low jitter performance: the voltage controlled oscillator (VCO) used in a phase-locked loop (PLL). Techniques are presented for circuit-level design of low jitter delay elements for use in ring oscillators, as well as relating the circuit-level characteristics to system-level performance. Although the emphasis is on time-domain (jitter) measures of oscillator p- formance, a simple method of translating performance to frequency domain (phase noise) measures is presented as well. Structure of this Book This book is divided into nine chapters. The diagram on the following page shows the relationship between material in each chapter as well as placement in the system-level vs. circuit-level design hierarchy. Wherever possible, - perimental veri cation is presented in the same chapter as the corresponding theoretical development, rather than being isolated in a separate chapter.