Wilhelm G. Spruth

The Design of a Microprocessor

• Broschiertes Buch

Produktbeschreibung

This text has been produced for the benefit of students in computer and infor mation science and for experts involved in the design of microprocessors. It deals with the design of complex VLSI chips, specifically of microprocessor chip sets. The aim is on the one hand to provide an overview of the state of the art, and on the other hand to describe specific design know-how. The depth of detail presented goes considerably beyond the level of information usually found in computer science text books. The rapidly developing discipline of designing complex VLSI chips, especially microprocessors, requires a significant extension of the state of the art. We are observing the genesis of a new engineering discipline, the design and realization of very complex logical structures, and we are obviously only at the beginning. This discipline is still young and immature, alternate concepts are still evolving, and "the best way to do it" is still being explored. Therefore it is not yet possibleto describe the different methods in use and to evaluate them. However, the economic impact is significant today, and the heavy investment that companies in the USA, the Far East, and in Europe, are making in gener ating VLSI design competence is a testimony to the importance this field is expected to have in the future. Staying competitive requires mastering and extending this competence.

Produktdetails

• Verlag: Springer, Berlin
• Softcover reprint of the original 1st ed. 1989
• Seitenzahl: 372
• Erscheinungstermin: 28. Januar 2012
• Englisch
• Abmessung: 242mm x 170mm x 21mm
• Gewicht: 635g
• ISBN-13: 9783642749186
• ISBN-10: 3642749186
• Artikelnr.: 36122644

Inhaltsangabe

'1. Introduction.- 1. Introduction.- 1.1. Overview.- 1.2. Structure of the Book.- 1.3. S/370 Architecture.- 1.4. Layered Processor Structure.- 2. Logic Design.- 2.1. Design Overview.- 2.1.1 Introduction.- 2.1.1.1 Design Goals.- 2.1.1.2 Processor Structure.- 2.1.2 Chip Set Description.- 2.1.2.1 Processing Unit (CPU) Chip.- 2.1.2.2 Memory Management Unit (MMU) Chip.- 2.1.2.3 Storage Controller (STC) Chip.- 2.1.2.4 Clock Chip.- 2.1.2.5 Control Store (CS) Chip.- 2.1.2.6 Floating Point Unit (FPU) Chip.- 2.1.3 Chip Interconnection Busses.- 2.1.4 Cache Timing Considerations.- 2.1.5 Miscellaneous.- 2.1.5.1 Reliability, Availability, Serviceability (RAS).- 2.1.5.2 System Measurement Interface (SMI).- 2.1.5.3 Other Processor Components.- 2.2. Processing Unit Chip.- 2.2.1 Design Considerations.- 2.2.2 Block Diagram Description.- 2.2.3 Modes of Operation.- 2.2.3.1 S/370 Mode.- 2.2.3.2 Micromode.- 2.2.3.3 Forced Operations.- 2.2.4 Pipelining.- 2.2.5 Data Local Store Layout.- 2.2.6 Micro Instructions.- 2.2.6.1 Data Local Store Addressing.- 2.2.6.2 Microinstructions Types and Formats.- 2.2.6.3 Reducing the Number of Branch Microinstructions.- 2.2.7 Data Flow Logic.- 2.2.7.1 ALU, Shift, Units and DLS.- 2.2.7.2 Bus Unit and Processor Bus Operations.- 2.2.8 Prefetch Buffer.- 2.2.9 Floating-Point Coprocessor Interface.- 2.3 Timer Support.- 2.3.1 Introduction to the Timer Functions.- 2.3.2 Format of the Timer Binary Counters.- 2.3.3 Functional Description and Block Diagram.- 2.3.4 Communication with the CPU.- 2.3.5 Programmable Clock Cycle Time.- 2.4. Memory Management Unit Chip.- 2.4.1 Overview.- 2.4.2 Storage Hierarchy Elements.- 2.4.2.1 Virtual Storage Addressing.- 2.4.2.2 Translation-Lookaside Buffer.- 2.4.2.3 Cache Operation.- 2.4.2.4 Key Store.- 2.4.2.5 Combined Operation.- 2.4.3 MMU Chip Data Flow.- 2.4.4 Array Macros.- 2.4.4.1 Translation-Lookaside Buffer (TLB).- 2.4.4.2 Cache Directory.- 2.4.4.3 Cache Array.- 2.4.4.4 Keystore.- 2.4.5 Storage Controller Interface.- 2.5. Storage Controller Chip.- 2.5.1 STC Chip Structure.- 2.5.1.1 Memory Control Unit.- 2.5.1.2 Error Correction Unit.- 2.5.1.3 STC Chip Interfaces.- 2.5.2 Memory Organization and Control.- 2.5.2.1 Overview.- 2.52.2 Memory Card.- 2.5.2.3 Memory Performance.- 2.5.2.4 Fetch Operation.- 2.5.2.5 Store Operation.- 2.5.3 Data Integrity.- 2.5.3.1 Refresh.- 2.5.3.2 ECC (Error Correction Codes).- 2.5.3.3 Complement Retry.- 2.5.3.4 Redundant Bit.- 2.5.3.5 Scrub.- 2.5.3.6 Address Fault Protection.- 2.5.4 Diagnostics.- 2.5.5 Personalization.- 2.6. Floating Point Coprocessor.- 2.6.1 General Description.- 2.6.2 Floating-Point Instructions and Data Format.- 2.6.3 FPU Interface and Communication.- 2.6.4 Chip Logical Description.- 2.6.4.1 Overview.- 2.6.4.2 Exponent Dataflow.- 2.6.4.3 Mantissa Dataflow.- 2.6.5 Reliability, Checking and Testing.- 2.6.5.1 Reliability.- 2.6.5.2 Checking.- 2.6.6 Performance.- 2.7. Bus Interface Chips.- 2.7.1 Overview.- 2.7.2 MBA Chip.- 2.7.3 BCU Chip.- 2.8. Clock Chip.- 2.8.1 Central Clock Generation Versus Distributed Clock Generation.- 2.8.2 Logical Implementation.- 2.8.3 Timing Tolerances, Reset and Checking.- 2.9. Clocking.- 2.9.1 Clock Signal Types.- 2.9.2 Clock Generation Flow.- 2.9.3 Clock Pulse Generation.- 2.9.4 Evaluation of the Clock Skews.- 2.9.5 Logic Chip Clock Distribution.- 2.9.5.1 Standàrd On-Chip Clock Distribution.- 2.9.5.2 High Performance On-Chip Clock Distribution.- 2.9.6 Evaluation of the Clocking Scheme.- 2.9.7 Clock Variation.- 2.10. Processor Bus.- 2.10.1 Processor Bus Connections.- 2.10.2 Processor Bus Implementation.- 2.10.3 Processor Bus Operation Example.- 2.11. Reliability, Availability, Serviceability.- 2.11.1 Overview.- 2.11.2 RAS Strategy and Requirements.- 2.11.3 Initial Chip Set Start and Loading.- 2.11.4 Error Detection.- 2.11.5 Machine Check Handling.- 2.11.6 Support Interface.- 2.11.6.1 Unit Support Interface Description.- 2.11.6