Temporal Logic in Specification
Altrincham, UK, April 8-10, 1987, Proceedings
Mitarbeit: Banieqbal, Benham; Barringer, Howard; Pnueli, Amir
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Comparing linear and branching time temporal logics.- Interleaving set temporal logic.- An expressive logic for a process algebra with silent actions.- Temporal logic with fixed points.- On the relation of programs and computations to models of temporal logic.- Specification and verification of concurrent programs by ?-automata.- MCTL ¿ An extension of CTL for modular verification of concurrent systems.- The model checking problem for concurrent systems with many similar processes.- Unified verification theory.- Specifying message passing systems requires extending temporal logic.- Extending ...
Comparing linear and branching time temporal logics.- Interleaving set temporal logic.- An expressive logic for a process algebra with silent actions.- Temporal logic with fixed points.- On the relation of programs and computations to models of temporal logic.- Specification and verification of concurrent programs by ?-automata.- MCTL ¿ An extension of CTL for modular verification of concurrent systems.- The model checking problem for concurrent systems with many similar processes.- Unified verification theory.- Specifying message passing systems requires extending temporal logic.- Extending interval logic to real time systems.- The prescription and description of state based systems.- Enforcing nondeterminism via linear time temporal logic specifications using hiding.- Specifying communicating systems with temporal logic.- Abstract object types: A temporal perspective.- Compositionality and modularity in process specification and design: A trace-state based approach.- Using temporal logic for prototyping: The design of a lift controller.- The declarative past and imperative future.
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