System level modeling of Phase Locked Loops - Paavle, Toivo
32,99 €
inkl. MwSt.
Versandkostenfrei*
Versandfertig in 6-10 Tagen
payback
16 °P sammeln
  • Broschiertes Buch

This work bases on the PhD thesis, defended by the author at Tallinn University of Technology in 2003. The work summarizes the main results of author's scientific work in the field of modeling and simulation of phase locked loops (PLLs). The book explains the modeling principles and presents the solutions of problems, for which the designed computer models and simulators were used. As a result, a set of parameters for adequate behavior of the PLL in respective applications is proposed. The scope of modeling and simulation is limited by the analog (classical) and mixed analog/digital structures…mehr

Andere Kunden interessierten sich auch für
Produktbeschreibung
This work bases on the PhD thesis, defended by the author at Tallinn University of Technology in 2003. The work summarizes the main results of author's scientific work in the field of modeling and simulation of phase locked loops (PLLs). The book explains the modeling principles and presents the solutions of problems, for which the designed computer models and simulators were used. As a result, a set of parameters for adequate behavior of the PLL in respective applications is proposed. The scope of modeling and simulation is limited by the analog (classical) and mixed analog/digital structures of the PLL, while two methods for system level modeling (phase-domain and signal-domain modeling) are treated. Dealing with different PLL topics makes the book somewhat eclectic, but helps to apprehend and recognize the benefits of using simple and fast running models as an alternative to expensive commercial software tools for behavioral simulation of PLLs. It might encourage the researches, engineers and students to use cheap general-purpose software for developing self-made models for the study of dynamics and exactness of performance as PLLs as well as other nonlinear dynamic systems.
Autorenporträt
Toivo Paavle graduated from Tallinn University of Technology(TUT)in 1975, and received the MSc and PhD degree in 1999 and 2003, respectively. His PhD research deals with design andsimulation of phase locked loops. He continues his research inthe field of systems simulation and signal processing at theCentre of Research Excellence CEBE at TUT.