Andere Kunden interessierten sich auch für
![Subthreshold Modeling of Submicron MOSFETs]( "Subthreshold Modeling of Submicron MOSFETs")
Subthreshold Modeling of Submicron MOSFETs32,99 €![Review of non conventional MOSFETs]( "Review of non conventional MOSFETs")
Review of non conventional MOSFETs39,99 €![Modelling of basic parameters for non-conventional MOSFETs]( "Modelling of basic parameters for non-conventional MOSFETs")
Modelling of basic parameters for non-conventional MOSFETs29,99 €![Subthreshold Surface Potential Model for Short-Channel Mosfet]( "Subthreshold Surface Potential Model for Short-Channel Mosfet")
Subthreshold Surface Potential Model for Short-Channel Mosfet23,99 €![A Subthreshold Reconfigurable Architecture for Harsh Environment]( "A Subthreshold Reconfigurable Architecture for Harsh Environment")
A Subthreshold Reconfigurable Architecture for Harsh Environment42,99 €![Digital Circuits Using Subthreshold Leakage Power Reduction Techniques]( "Digital Circuits Using Subthreshold Leakage Power Reduction Techniques")
Digital Circuits Using Subthreshold Leakage Power Reduction Techniques32,99 €![Étude du potentiel de surface sous le seuil des MOSFETs]( "Étude du potentiel de surface sous le seuil des MOSFETs")
Étude du potentiel de surface sous le seuil des MOSFETs29,99 €
In this book the main focus has been on the modeling and the influence of depletion layers around the source and the drain regions on the sub-threshold characteristics of a short channel MOS transistor with uniformly-doped channel. An analytical model for sub-threshold surface potential in a short channel MOS transistor has been developed by solving the pseduo-2D Poisson's equation, formulated by applying Gauss's law to a rectangular box in the channel covering the entire depletion layer depth. The model has been able to predict an increased influence of the junction depletion regions for smaller channel length and/or higher drain/source bias voltages due to increased charge sharing. The same model is applied to find the sub threshold surface potential for Double Halo MOSFETs. The shrinking of device dimension leads to reduction of gate oxide thickness. As a result of this the undesirable hot electron effect and the gate tunneling current is increased. In order to overcome this drawback high-k material are used instead of silicon dioxide as the insulating material underneath the gate. These modeling will prove to be beneficial and help in further research work in the future.