Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators explored.
Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators explored.
Anirban Sengupta is an associate professor in computer science and engineering at Indian Institute of Technology (I.I.T) Indore, India, where he directs the research lab on CAD for Consumer Electronics Hardware Device Security & Reliability. He has written over 235 publications. He is a distinguished lecturer and distinguished visitor of multiple IEEE Societies, an elected fellow of the British Computer Society and a fellow of the IET.
Inhaltsangabe
* Chapter 1: Introduction: secured and optimized hardware accelerators for DSP and image processing applications * Chapter 2: Cryptography-driven IP steganography for DSP hardware accelerators * Chapter 3: Double line of defence to secure JPEG codec hardware for medical imaging systems * Chapter 4: Integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators * Chapter 5: Multimodal hardware accelerators for image processing filters * Chapter 6: Fingerprint biometric for securing hardware accelerators * Chapter 7: Key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators * Chapter 8: Designing a secured N-point DFT hardware accelerator using obfuscation and steganography * Chapter 9: Structural transformation-based obfuscation using pseudo-operation mixing for securing data-intensive IP cores
* Chapter 1: Introduction: secured and optimized hardware accelerators for DSP and image processing applications * Chapter 2: Cryptography-driven IP steganography for DSP hardware accelerators * Chapter 3: Double line of defence to secure JPEG codec hardware for medical imaging systems * Chapter 4: Integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators * Chapter 5: Multimodal hardware accelerators for image processing filters * Chapter 6: Fingerprint biometric for securing hardware accelerators * Chapter 7: Key-triggered hash-chaining-based encoded hardware steganography for securing DSP hardware accelerators * Chapter 8: Designing a secured N-point DFT hardware accelerator using obfuscation and steganography * Chapter 9: Structural transformation-based obfuscation using pseudo-operation mixing for securing data-intensive IP cores
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