Performance Analysis of Modified Karatsuba Multiplier and Application
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Finite Field arithmetic is becoming increasingly a very prominent solution for calculations in many VLSI applications. The fundamental Karatsuba Multiplication (KM) algorithm is based on the idea of the divide-and-conquer rule which was the first algorithm to accomplish polynomial multiplication in the GF field. Compared to the well-known Schoolbook method, the Karatsuba Algorithm saves the multiplications of the partial products at the cost of extra additions. Here six different multipliers (Mastrovito Multiplier, Paar-Roelse multiplier, Massey- Omura Multiplier, Hasan-Masoleh Multiplier, Ber...
Finite Field arithmetic is becoming increasingly a very prominent solution for calculations in many VLSI applications. The fundamental Karatsuba Multiplication (KM) algorithm is based on the idea of the divide-and-conquer rule which was the first algorithm to accomplish polynomial multiplication in the GF field. Compared to the well-known Schoolbook method, the Karatsuba Algorithm saves the multiplications of the partial products at the cost of extra additions. Here six different multipliers (Mastrovito Multiplier, Paar-Roelse multiplier, Massey- Omura Multiplier, Hasan-Masoleh Multiplier, Berlekamp Multiplier, and Karatsuba Multiplier) are compared with their performance based on complexity and delay. This book presents a modified multiplication algorithm based on the Karatsuba Multiplication algorithm for the composite finite field in GF(24) & GF(28). To optimize the Karatsuba Multiplication algorithm, the product terms are split into two alternative forms. This Modified architecture saves the computation time and area in VLSI implementations more than any other existing algorithms. The work is done using the Xilinx-based Spartan & Vertex device family.
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