This book covers the important aspects of Network-on-Chip (NoC) design, including communication infrastructure design, communication methodology and evaluation framework. It also focuses on other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis and 3-D NoC design.
This book covers the important aspects of Network-on-Chip (NoC) design, including communication infrastructure design, communication methodology and evaluation framework. It also focuses on other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis and 3-D NoC design.
Santanu Kundu received his BTech in instrumentation engineering from Vidyasagar University, Medinipur, West Bengal, India, in 2002. He received his MTech in instrumentation and electronics engineering from Jadavpur University, Kolkata, West Bengal, India, in 2006. Immediately after that he joined the electronics and electrical communication engineering department at the Indian Institute of Technology, Kharagpur, West Bengal, India. He received his PhD in 2011. His research interests include network-on-chip architecture design in 2D and 3D environments, performance and cost evaluation, signal integrity in nanometer regime, fault-tolerant schemes, and power-performance-reliability trade-off. He is currently a system-on-chip (SoC) design engineer at LSI India R&D Pvt. Ltd., Bangalore, Karnataka, India. Santanu Chattopadhyay received his BE in computer science and technology from Calcutta University (BE College), Kolkata, West Bengal, in 1990. In 1992 and 1996, he received his MTech in computer and information technology and PhD in computer science and engineering, respectively, both from the Indian Institute of Technology (IIT), Kharagpur, West Bengal, India. He is currently a professor in the electronics and electrical communication engineering department at the IIT, Kharagpur. He has contributed to more than 100 publications in refereed international journals and conferences. He has also coauthored and written several textbooks, and is a member of the editorial board of the journal IET Circuits, Devices and Systems.
Inhaltsangabe
Introduction. Interconnection Networks in Network on Chip. Architecture Design of Network on Chip. Evaluation of Network on Chip Architectures. Application Mapping on Network on Chip. Low Power Techniques for Network on Chip. Signal Integrity and Reliability of Network on Chip. Testing of Network on Chip Architectures. Application Specific Network on Chip Synthesis. Reconfigurable Network on Chip Design. Three Dimensional Integration of Network on Chip. Conclusions and Future Trends. References. Index.
Introduction. Interconnection Networks in Network on Chip. Architecture Design of Network on Chip. Evaluation of Network on Chip Architectures. Application Mapping on Network on Chip. Low Power Techniques for Network on Chip. Signal Integrity and Reliability of Network on Chip. Testing of Network on Chip Architectures. Application Specific Network on Chip Synthesis. Reconfigurable Network on Chip Design. Three Dimensional Integration of Network on Chip. Conclusions and Future Trends. References. Index.
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