Low-Cost Congestion Management for NOC
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Rapid innovations in circuit integration technology have successfully integrated billions of transistors on a single chip. The advancement in IC technology has put the challenge of extracting the maximum performance gain from additional resources. In recent times, computer architects have exhorted many-core design to meet next generation computation needs. Chips, equipped with a large number of cores, bracing dynamic parallelism and modest power usage are proposed to meet future computation needs. Intriguingly, the performance of the many-core architecture greatly relies on the competence of t...
Rapid innovations in circuit integration technology have successfully integrated billions of transistors on a single chip. The advancement in IC technology has put the challenge of extracting the maximum performance gain from additional resources. In recent times, computer architects have exhorted many-core design to meet next generation computation needs. Chips, equipped with a large number of cores, bracing dynamic parallelism and modest power usage are proposed to meet future computation needs. Intriguingly, the performance of the many-core architecture greatly relies on the competence of the on-chip interconnection network. Networks-on-Chip (NoCs) has emerged as the backbone of many-core architectures. Nevertheless, poor network performance due to congestion could become a major hindrance in the future multi-core designs. In the present research, we investigate the causes of congestion in NoCs and facilitate ways to mitigate the performance threat. In particular, the focus ofthis research is on providing cost-effective congestion management solutions suitable for NoCs.
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