High Speed Signature Detection Architectures for Network Applications
FPGA based Reconfigurable Architectures
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The continuous growth in the Internet's size, the amount of data traffic, and the complexity of processing the traffic give rise to new challenges in building high performance network devices. One of the most fundamental tasks performed by these devices is detecting the signature for predefined keys. Address lookup, packet classification, and deep packet inspection are some of the operations which involve Signature Detection Technique which is typically a part of the packet forwarding mechanism, and may create a performance bottleneck. More than that software based SDT algorithms are normally ...
The continuous growth in the Internet's size, the amount of data traffic, and the complexity of processing the traffic give rise to new challenges in building high performance network devices. One of the most fundamental tasks performed by these devices is detecting the signature for predefined keys. Address lookup, packet classification, and deep packet inspection are some of the operations which involve Signature Detection Technique which is typically a part of the packet forwarding mechanism, and may create a performance bottleneck. More than that software based SDT algorithms are normally slow which can not match with today's high speed network traffic. Therefore, fast and resource efficient hardware architectures are required. Most commonly used hardware based techniques for such signature detection are Content addressable Memory and Bloom Filter. While CAM can offer very fast search, it is expensive and consumes a large amount of power. A Bloom filter is used to represent aset of bit-strings compactly and support set membership queries. Hence, designing high performance, power-efficient and high-speed signature detection techniques has received a great deal of attention
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