Design Of High Speed and Low Power Multiplier - Gopalakrishnan, S.;Sasi, G.
26,99 €
inkl. MwSt.
Versandkostenfrei*
Versandfertig in 6-10 Tagen
payback
13 °P sammeln
  • Broschiertes Buch

Power dissipation is recognized as a critical parameter in modern VLSI field. To produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary.The increasing speed and complexity of today's designs implies a significant increase in the power consumption of very-large-scale integration (VLSI) chips. Multiplication is an important part of real-time digital signal processing (DSP) applications ranging from digital filtering to image processing.The Spurious Power Suppression Technique (SPST) uses a detection logic circuit to detect the effective data range of arithmetic units.…mehr

Andere Kunden interessierten sich auch für
Produktbeschreibung
Power dissipation is recognized as a critical parameter in modern VLSI field. To produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary.The increasing speed and complexity of today's designs implies a significant increase in the power consumption of very-large-scale integration (VLSI) chips. Multiplication is an important part of real-time digital signal processing (DSP) applications ranging from digital filtering to image processing.The Spurious Power Suppression Technique (SPST) uses a detection logic circuit to detect the effective data range of arithmetic units.
Autorenporträt
Dr.S.Gopalakrishnan having more than a decade of experience in Academic and research.He obtained his doctoral degree in Management sciences from Anna University and M.B.A from Bharathiyar University,India.Dr.D.Muruganandam having more than two decades of experience in academic and research.He obtained his doctoral degree in Management.