Design and Synthesis of Custom IP in VLSI - Divya, Bejagam;Malipatil, Dr.Somashekhar;Muddapu, R. Madhuri
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In this work, we have designed custom IP for First in First out (FIFO) with reduced power dissipation and with high speed. The Vivado Design Suite has an IP-centric design flow that helps us speedily turn designs and algorithms into reusable IP. The IP Catalog of Vivado is an integrated IP repository that provides the framework for the IP-centric design flow. This Catalog consolidates IP from all sources including Xilinx® IP. The Vivado IP packager tool is a distinctive design reuse feature, which is based upon the IP-XACT standard. The IP packager tool provides with the capability to package…mehr

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Produktbeschreibung
In this work, we have designed custom IP for First in First out (FIFO) with reduced power dissipation and with high speed. The Vivado Design Suite has an IP-centric design flow that helps us speedily turn designs and algorithms into reusable IP. The IP Catalog of Vivado is an integrated IP repository that provides the framework for the IP-centric design flow. This Catalog consolidates IP from all sources including Xilinx® IP. The Vivado IP packager tool is a distinctive design reuse feature, which is based upon the IP-XACT standard. The IP packager tool provides with the capability to package a design at any step of the design flow and organize the core as system-level IP. This project is concentrating on creating and packaging custom IP (FIFO). The proposed design of custom IP (FIFO) is simulated and synthesized in Xilinx Vivado 19.1.
Autorenporträt
Mme Bejagam Divya, ingénieur de projet (base contractuelle), DRDO RCI, Hyderabad, Telangana. Dr. Somashekhar Malipatil, professeur adjoint, Malla Reddy Engineering College & Management Sciences, Medchal, Hyderabad, Telangana. Mme R. Madhuri Muddapu, Scientist 'C', DRDO RCI, Hyderabad, Telangana.