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As the complexity of hardware designs is increasing rapidly day-by-day with the introduction of newer technologies, it is very important to ensure the correctness of these designs. During verification, the primary objective is to measure the coverage of the verified functionalities of a design and, hence, indicate the completeness of the verification effort. Since it is widely believed that the future of design verification lies in the co-existence of both simulation and formal property verification techniques, unifying the coverage goals for both of these contrasting verification technologies is becoming very essential. The inter-relationships among the simulation test plans, assertions and test benches are very important to the success of verification, but they are often loosely tied. In this monograph, we attempt to relate then more formally to achieve a potentially better strategy for cohesive coverage management in verification. We believe that the methods presented in this monograph will lead to wider adoption of the cohesive coverage management techniques in the design validation flow.