Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design

Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design

A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach

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With the end of Dennard scaling and Moore's law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and se...