Advanced Parallel Processing Technologies

8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009 Proceedings
Herausgegeben:Dou, Yong; Gruber, Ralf; Joller, Josef

• Broschiertes Buch

Produktbeschreibung

th This volume contains the papers presented at the 8 International Conference on - vanced Parallel Processing Technologies, APPT 2009. This series of conferences originated from collaborations between researchers from China and Germany and has evolved into an international conference for reporting advances in parallel processing technologies. APPT 2009 addressed the entire gamut of related topics, ranging from the architectural aspects of parallel computer hardware and system software to the applied technologies for novel applications. For this conference, we received over 76 full submissions from researchers all over the world. All the papers were peer reviewed in depth and qualitatively graded on their relevance, originality, significance, presentation, and the overall appropriateness for their acceptance. Any concerns raised were discussed by the Program Committee. The Organizing Committee did an excellent job in selecting 36 papers for presen- tion. In short, the papers included here represent the forefront of research from China, Switzerland, Germany, and other countries.

Produktdetails

• Theoretical Computer Science and General Issues 5737
• Verlag: Springer / Springer Berlin Heidelberg / Springer, Berlin
• Artikelnr. des Verlages: 12736133, 978-3-642-03643-9
• 2009
• Seitenzahl: 492
• Erscheinungstermin: 6. August 2009
• Englisch
• Abmessung: 235mm x 155mm x 27mm
• Gewicht: 739g
• ISBN-13: 9783642036439
• ISBN-10: 3642036430
• Artikelnr.: 26610200

Inhaltsangabe

Architecture.
A Fast Scheme to Investigate Thermal
Aware Scheduling Policy for Multicore Processors.
Dealing with Traffic
Area Trade
Off in Direct Coherence Protocols for Many
Core CMPs.
An Efficient Lightweight Shared Cache Design for Chip Multiprocessors.
A Novel Cache Organization for Tiled Chip Multiprocessor.
A Performance Model for Run
Time Reconfigurable Hardware Accelerator.
SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework.
Implementation of Rotation Invariant Multi
View Face Detection on FPGA.
The Design and Evaluation of a Selective Way Based Trace Cache.
A Fine
Grained Pipelined Implementation for Large
Scale Matrix Inversion on FPGA.
L1 Collective Cache: Managing Shared Data for Chip Multiprocessors.
Graphical Processing Unit.
Efficient Multiplication of Polynomials on Graphics Hardware.
Performance Optimization Strategies of High Performance Computing on GPU.
A Practical Approach of Curved Ray Prestack Kirchhoff Time Migration on GPGPU.
GCSim: A GPU
Based Trace
Driven Simulator for Multi
level Cache.
A Hybrid Parallel Signature Matching Model for Network Security Applications Using SIMD GPU.
Grid.
HPVZ: A High Performance Virtual Computing Environment for Super Computers.
High Performance Support of Lustre over Customized HSNI for HPC.
ViroLab Security and Virtual Organization Infrastructure.
E2EDSM: An Edge
to
Edge Data Service Model for Mass Streaming Media Transmission.
Grid Scheduling.
Iso
Level CAFT: How to Tackle the Combination of Communication Overhead Reduction and Fault Tolerance Scheduling.
MaGate Simulator: A Simulation Environment for a Decentralized Grid Scheduler.
Mobile Applications.
A Distributed Shared Memory Architecture for Occasionally Connected Mobile Environments.
Time
Adaptive Vertical Handoff Triggering Methods for Heterogeneous Systems.
Energy
Saving Topology Control for Heterogeneous Ad Hoc Networks.
Parallel Applications.
Computational Performance of a Parallelized Three
Dimensional High
Order Spectral Element Toolbox.
Research on Evaluation of Parallelization on an Embedded Multicore Platform.
MapReduce
Based Pattern Finding Algorithm Applied in Motif Detection for Prescription Compatibility Network.
Parallelization of the LEMan Code with MPI and OpenMP.
The Recursive Dual
Net and Its Applications.
Parallelization Strategies for Mixed Regular
Irregular Applications on Multicore
Systems.
Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices.
Large Matrix Multiplication on a Novel Heterogeneous Parallel DSP Architecture.
Implementing Fast Packet Filters by Software Pipelining on x86 Processors.
Parallel Libraries.
OSL: Optimized Bulk Synchronous Parallel Skeletons on Distributed Arrays.
Performance.
Evaluating SPLASH
2 Applications Using MapReduce.
MPTD: A Scalable and Flexible Performance Prediction Framework for Parallel Systems.