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Abstract: A process-based model (UFET) for deep-submicron bulk-silicon MOSFETs is developed and verified with numerical device simulations and measured data. The charge-based model is physical with accountings for the predominant short-channel (e.g., charge sharing, drain-induced threshold reduction and velocity saturation) and extremely scaled-technology (i.e., energy quantization and polysilicon-gate depletion) effects in MOSFETs. The key to UFET is the characterization of the bias-dependent two-dimensional regions near the source/ drain junctions which can extend over a significant fraction of the metallurgical channel length. When these two-dimensional regions near the junctions are modeled, the physical charge-sheet model can be applied to the remaining "quasi-two- dimensional" channel length to define the channel current and terminal charges, without resorting to empiricism to account for the short-channel effects. Special attention paid to continuity in the derivation of the model formalism yields a physical C-infinity model applicable to analog and digital CMOS circuit design. The small number of physical, process-based parameters simplifies the model calibration, and renders the model suitable for predictive device/circuit simulation, statistical simulations and circuit sensitivity analyses based on known or presumed process variations. Dissertation Discovery Company and University of Florida are dedicated to making scholarly works more discoverable and accessible throughout the world. This dissertation, "A Physical MOSFET Model Applicable to Extremely Scaled CMOS IC Design" by Douglas Aaron Weiser, was obtained from University of Florida and is being sold with permission from the author. A digital copy of this work may also be found in the university's institutional repository, IR@UF. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation.