A Dual Address Space Architecture
Implementation and Evaluation
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Parallel computer architectures, while difficult to program, are now a fact of life in scientific computing and, increasingly, computing in general. While a hardware supported shared address space offers programmability advantages and better performance for fine-grained communication, the very mechanisms that create those advantages appear to prevent the machines that use them from scaling to large numbers of processors. This book proposes changes to a hardware-based DSM architecture that allow software to use two address spaces to gain the scalability of distributed architectures and retain t...
Parallel computer architectures, while difficult to program, are now a fact of life in scientific computing and, increasingly, computing in general. While a hardware supported shared address space offers programmability advantages and better performance for fine-grained communication, the very mechanisms that create those advantages appear to prevent the machines that use them from scaling to large numbers of processors. This book proposes changes to a hardware-based DSM architecture that allow software to use two address spaces to gain the scalability of distributed architectures and retain the benefits of the shared address space architecture. The Dual Address Space Architecture provides both an efficient mechanism for enabling increased user and compiler control over data consistency and data locality, and a high-level interface for programmers to conceptualize and take advantage of the mechanism. The Dual Address Space Architecture thus provides users and compilers an efficient means, particularly appropriate to the structure of scientific applications, of keeping data consistent and local, enabling improved performance over current global address space implementations.
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