Physical Design Essentials - Golshan, Khosrow
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Physical Design Essentials explains the basic steps required in the physical design of Application Specific Integrated Circuits (ASICs). The subject matter presentation follows the industry-common ASIC physical design flow.
Topics covered include:
Basic standard cell design, transistor-sizing, and layout styles
Linear, non-linear, and polynomial characterization
Physical design constraints and floor planning styles
Algorithms used for placement
Clock tree synthesis
Algorithms used for global and detailed routing
Parasitic extraction
Functional timing and physical…mehr

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Produktbeschreibung
Physical Design Essentials explains the basic steps required in the physical design of Application Specific Integrated Circuits (ASICs). The subject matter presentation follows the industry-common ASIC physical design flow.

Topics covered include:

Basic standard cell design, transistor-sizing, and layout styles

Linear, non-linear, and polynomial characterization

Physical design constraints and floor planning styles

Algorithms used for placement

Clock tree synthesis

Algorithms used for global and detailed routing

Parasitic extraction

Functional timing and physical methods of verification

Testing Techniques

Physical Design Essentials is written for professional design engineers who need to be conversant with all aspects of ASIC design implementation: device processes, library development, place-and-route algorithms,verification, and testing.
Autorenporträt
Physical Design Essentials is arranged in a format that follows the industry-common ASIC physical design flow. Its target audience is today s physical design engineers or professionals in the ASIC area that are expected to be conversant with all aspects of ASIC design implementation stages including device processes, library development, place-and-route algorithms, verification and testing. It begins with general concepts of an ASIC library, then covers floor planning, placement, routing, verification, and finally, testing.
Topics covered include: Basic standard cell design, transistor-sizing, and layout styles; Linear, non-linear, and polynomial characterization; Physical design constraints and floor planning styles; Algorithms used for placement Clock Tree Synthesis; Algorithms used for global and detailed routing; parasitic extraction; Functional timing and physical methods of verification; Electronic Testing.