Reconfigurable Computing: Architectures, Tools and Applications - Diniz, Pedro C. (Volume ed.) / Marques, Eduardo / Bertels, Koen / Fernandes, Marcio Merino / Cardoso, Joao M.P.
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  • Broschiertes Buch

This book constitutes the refereed proceedings of the Third International Workshop on Applied Reconfigurable Computing, ARC 2007, held in Mangaratiba, Brazil, in March 2007. The 27 full papers and 10 short papers presented together with a late-comer contribution from ARC 2006 are organized in topical sections on architectures, mapping techniques and tools, arithmetic, and applications. …mehr

Produktbeschreibung
This book constitutes the refereed proceedings of the Third International Workshop on Applied Reconfigurable Computing, ARC 2007, held in Mangaratiba, Brazil, in March 2007. The 27 full papers and 10 short papers presented together with a late-comer contribution from ARC 2006 are organized in topical sections on architectures, mapping techniques and tools, arithmetic, and applications.
  • Produktdetails
  • Lecture Notes in Computer Science Vol.4419
  • Verlag: Springer, Berlin
  • Artikelnr. des Verlages: 12035847
  • 2007
  • Seitenzahl: 412
  • Erscheinungstermin: 19. März 2007
  • Englisch
  • Abmessung: 235mm x 155mm x 22mm
  • Gewicht: 576g
  • ISBN-13: 9783540714309
  • ISBN-10: 3540714308
  • Artikelnr.: 22716172
Autorenporträt
Pedro C. Diniz, Instituto Superior Técnico (IST)/INESC-ID, Porto Salvo, Portugal / Eduardo Marques, Universidade de Sao Paulo, Brazil / Koen Bertels, Delft University of Technology, CD Delft, The Netherlands / Marcio Merino Fernandes, Universidade Metodista de Piracicaba, Brazil / Joao M.P. Cardoso, Instituto Superior Técnico, Lisbon, Portugal
Inhaltsangabe
Architectures [Regular Papers].- Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array.- A Configurable Multi-ported Register File Architecture for Soft Processor Cores.- MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture.- Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture.- Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs.- Systematic Customization of On-Chip Crossbar Interconnects.- Authentication of FPGA Bitstreams: Why and How.- Architectures [Short Papers].- Design of a Reversible PLD Architecture.- Designing Heterogeneous FPGAs with Multiple SBs.- Mapping Techniques and Tools [Regular Papers].- Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations.- Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware.- Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations.- A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions.- Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping.- The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.- Hardware/Software Codesign for Embedded Implementation of Neural Networks.- Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues.- Mapping Techniques and Tools [Short Papers].- About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations.- Arithmetic [Regular Papers].- Switching Activity Models for Power Estimation in FPGA Multipliers.- Multiplication over on FPGA: A Survey.- A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm.- A Fast Finite Field Multiplier.- Applications [Regular Papers].- Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image