This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.
This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Artikelnr. des Verlages: 80027337, 978-1-4614-0871-0
2012
Seitenzahl: 192
Erscheinungstermin: 21. Oktober 2011
Englisch
Abmessung: 241mm x 160mm x 16mm
Gewicht: 472g
ISBN-13: 9781461408710
ISBN-10: 1461408717
Artikelnr.: 33617276
Inhaltsangabe
Introduction; Related work; Background; Statistical Regression Based Power Models; Statistical Regression Based Power Models for FPGAs; High Level Simulation Directed RTL Power Estimation; Applying Verification Collaterals for Accurate Power Estimation; Architectural Selection using High Level Synthesis; Power Reduction using High-Level Clock-gating; Model-Checking to exploit Sequential Clock-Gating; Power model to facilitate aggressive reduction; Coprocessor Design Space Exploration using High Level Synthesis.
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.
Introduction; Related work; Background; Statistical Regression Based Power Models; Statistical Regression Based Power Models for FPGAs; High Level Simulation Directed RTL Power Estimation; Applying Verification Collaterals for Accurate Power Estimation; Architectural Selection using High Level Synthesis; Power Reduction using High-Level Clock-gating; Model-Checking to exploit Sequential Clock-Gating; Power model to facilitate aggressive reduction; Coprocessor Design Space Exploration using High Level Synthesis.
Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.
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