Digital VLSI Systems Design - Ramachandran, Seetharaman
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This book provides step-by-step guidance on how to design VLSI systems using Verilog. It shows the way to design systems that are device, vendor and technology independent. Coverage presents new material and theory as well as synthesis of recent work with complete Project Designs using industry standard CAD tools and FPGA boards. The reader is taken step by step through different designs, from implementing a single digital gate to a massive design consuming well over 100,000 gates. All the design codes developed in this book are Register Transfer Level (RTL) compliant and can be readily used or amended to suit new projects.…mehr

Produktbeschreibung
This book provides step-by-step guidance on how to design VLSI systems using Verilog. It shows the way to design systems that are device, vendor and technology independent. Coverage presents new material and theory as well as synthesis of recent work with complete Project Designs using industry standard CAD tools and FPGA boards. The reader is taken step by step through different designs, from implementing a single digital gate to a massive design consuming well over 100,000 gates. All the design codes developed in this book are Register Transfer Level (RTL) compliant and can be readily used or amended to suit new projects.
  • Produktdetails
  • Verlag: Springer Netherlands; Springer
  • Artikelnr. des Verlages: 978-94-017-8277-7
  • 2007
  • Seitenzahl: 732
  • Erscheinungstermin: 18. September 2014
  • Englisch
  • Abmessung: 235mm x 155mm x 38mm
  • Gewicht: 1104g
  • ISBN-13: 9789401782777
  • ISBN-10: 9401782776
  • Artikelnr.: 41531959
Autorenporträt
Dr. S. Ramachandran is a project officer in the Electrical Engineering Department at the Indian Institute of Technology, Madras. He has a wide industrial and teaching experience, having worked both in India and USA, designing systems and teaching/guiding students based on FPGAs and Microprocessors. His research interests include developing algorithms, architectures and implementations on FPGAs/ASICs for Video Processing, DSP applications, reconfigurable computing, open loop control systems, etc. He is the recipient of the Best Design Award at VLSI Design 2000, International Conference held at Calcutta, India. He has a number of papers in International Journals and Conferences. He has completed a video course on Digital VLSI System Design along with Prof. S. Srinivasan.
Inhaltsangabe
Preface Chapter 1 Introduction to Digital VLSI Systems Design. 1.1 Evolution of VLSI Systems. 1.2 Applications of VLSI Systems. 1.3 Processor based Systems. 1.4 Embedded Systems. 1.5 FPGA based Systems. 1.6 Digital System Design using FPGAs. 1.7 Reconfigurable Systems using FPGA. 1.8 Scope of the Book. Chapter 2 Review of Digital Systems Design. 2.1 Numbering Systems. 2.2 Twos Complement Addition/Subtraction. 2.3 Codes. 2.4 Boolean Algebra. 2.5 Boolean Functions using Minterms and Maxterms. 2.6 Logic Gates. 2.7 The Karnaugh MAP Method of Optimization of Logic Circuits. 2.8 Combination Circuits. 2.9 Arithmetic Logic Unit. 2.10 Programmable Logic Devices. 2.11 Sequential Circuits. 2.12 Random Access Memory (RAM). 2.13 Clock Parameters and Skew. 2.14 Setup, Hold and Propagation Delay Times in a Register. 2.15 Digital System Design using SSI/MSI Components. 2.16. Algorithmic State Machine. 2.17 Digital System Design Using ASM Chart and PAL.
Chapter 3 Design of Combinational and Sequential Circuits using Verilog. 3.1 Introduction to Hardware Design Language. 3.2 Design of Combinational Circuits. 3.3 Verilog Modeling of Sequential Circuits. 3.4 Coding Organization. Chapter 4 Writing a Test Bench for the Design. 4.1 Modeling a Test Bench. 4.2 Test Bench for Combinational Circuits. 4.3 Test Bench for Sequential Circuits. Chapter 5 RTL Coding Guidelines. 5.1 Separation of Combinational and Sequential Circuits. 5.2 Synchronous Logic. 5.3 Synchronous Flip-flop. 5.4 Realization of Time Delays. 5.5 Elimination of Glitches using Synchronous Circuits. 5.6 Hold Time Violation in Asynchronous Circuits. 5.7 RTL Coding Style. Chapter 6 Simulation of Designs - Modelsim Tool. 6.1 VLSI Design Flow. 6.2 Design Methodology. 6.3 Simulation using Modelsim. Chapter 7 Synthesis of Designs - Synplify Tool. 7.1 Synthesis. 7.2 Analysis of Design Examples using Synplify Tool. 7.3 Viewing Verilog Code as RTLSchematic Circuit Diagrams. 7.4 Optimization Effected in Synopsys Full and Parallel cases. 7.5 Performance comparison of FPGAs of two vendors for a Design. 7.6 Fixing Compilation Errors in Modelsim and Synplify Tools. 7.7 Synplify Command Summary. Chapter 8 Place and Route and Back annotation - Xilinx Tool. 8.1 Xilinx Place and Route Tool - Design Manager. 8.2 Xilinx Place and Route Command summary. 8.3 Place and Route and Back Annotation using Xilinx Project Navigator. Chapter 9 Design of Memories. 9.1 On-chip Dual Address ROM Design. 9.2 Single Address ROM Design. 9.3 On-Chip Dual RAM Design. 9.4 External Memory Controller Design. Chapter 10 Arithmetic Circuit Designs. 10.1 Digital Pipelining. 10.2 Partitioning of a Design. 10.3 Signed Adder Design. 10.4 Multiplier Design. Chapter 11 Development of Algorithms and Verification using High Level Languages. 11.1 2D-Discrete Cosine Transform and Quantization. 11.2 Automatic Quality Control Scheme for Image Compression. 11.3 Fast Motion Estimation Algorithm for Real-time Video Compression. Chapter 12 Architectural