- Gebundenes Buch
- Merkliste
- Auf die Merkliste
- Bewerten Bewerten
- Teilen
- Produkt teilen
- Produkterinnerung
- Produkterinnerung
Thema dieses Buches sind elektrostatische Entladungseffekte (ESD) in integrierten Siliciumschaltkreisen, die sich zu einem wesentlichen Problem der modernen hochintegrierten Schaltungen mit Strukturbreiten in Sub-Mikrometer-Dimensionen entwickelt haben. Diese 2. Auflage des klassischen Handbuchs liefert einen kompletten Überblick über alle Aspekte des ESD und die unmittelbaren Folgerungen für Entwurf und Entwicklung neuer Schaltkreise und Technologien. Die Hälfte des Materials wurde neu aufgenommen. das Autorenteam wurde um drei international anerkannte Experten erweitert.
Andere Kunden interessierten sich auch für
- Joseph T. DiBenePower Integrity152,99 €
- Raminderpal Singh (Hrsg.)Signal Integrity Effects in Custom IC and ASIC Designs213,99 €
- Alan B. GrebeneBipolar and Mos Analog Integrated Circuit Design152,99 €
- Ravender GoyalHigh-Frequency Analog Integrated Circuit Design268,99 €
- Samiha MouradPrinciples of Testing Electronic Systems187,99 €
- Behzad RazaviDesign of Integrated Circuits for Optical Communications146,99 €
- Peter ConradiReuse in Electronic Design287,99 €
-
-
-
Thema dieses Buches sind elektrostatische Entladungseffekte (ESD) in integrierten Siliciumschaltkreisen, die sich zu einem wesentlichen Problem der modernen hochintegrierten Schaltungen mit Strukturbreiten in Sub-Mikrometer-Dimensionen entwickelt haben. Diese 2. Auflage des klassischen Handbuchs liefert einen kompletten Überblick über alle Aspekte des ESD und die unmittelbaren Folgerungen für Entwurf und Entwicklung neuer Schaltkreise und Technologien. Die Hälfte des Materials wurde neu aufgenommen. das Autorenteam wurde um drei international anerkannte Experten erweitert.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Hinweis: Dieser Artikel kann nur an eine deutsche Lieferadresse ausgeliefert werden.
Produktdetails
- Produktdetails
- Verlag: Wiley & Sons
- 2. Aufl.
- Seitenzahl: 424
- Erscheinungstermin: 22. Mai 2002
- Englisch
- Abmessung: 250mm x 175mm x 27mm
- Gewicht: 932g
- ISBN-13: 9780471498711
- ISBN-10: 0471498718
- Artikelnr.: 09401718
- Verlag: Wiley & Sons
- 2. Aufl.
- Seitenzahl: 424
- Erscheinungstermin: 22. Mai 2002
- Englisch
- Abmessung: 250mm x 175mm x 27mm
- Gewicht: 932g
- ISBN-13: 9780471498711
- ISBN-10: 0471498718
- Artikelnr.: 09401718
E. Ajith Amerasekera is the author of ESD in Silicon Integrated Circuits, 2nd Edition, published by Wiley. Charvaka Duvvury is the author of ESD in Silicon Integrated Circuits, 2nd Edition, published by Wiley.
Preface 1. Introduction Background The ESD Problem Protecting against ESD
Outline of the Book 2. ESD Phenomenon Introduction Electrostatic Voltage
Discharge ESD Stress Models 3. Test Methods Introduction Human Body Model
(HBM) Machine Model (MM) Charged Device Model (CDM) Socket Device Model
(SDM) Metrology, Calibration, Verification Transmission Line Pulsing (TLP)
Failure Criteria Summary 4 Physics and Operation of ESD Protection Circuits
Introduction Resistors Diodes Transistor Operation Transistor Operation
Under ESD Conditions Electrothermal Effects SCR Operation Conclusion 5 ESD
Protection Design Concepts and Strategy The Qualities of Good ESD
Protection ESD Protection Design Methods Selecting an ESD Strategy Summary
6 Design and Layout Requirements Introduction Thick Field Device NMOS
Transistors (FPDs) Gate-Coupled NMOS (GCNMOS) Gate Driven nMOS (GDNMOS) SCR
Protection Device ESD Protection Design Synthesis Total Input Protection
ESD Protection Using Diode-Based Devices Power Supply Clamps BiPolar and
BiCMOS Protection Circuits Summary 7 Advanced Protection Design
Introduction PNP Driven NMOS (PDNMOS) Substrate Triggered NMOS (STNMOS)
NMOS Triggered NMOS (NTNMOS) ESD for Mixed Voltage I/O CDM Protection SOI
Technology High Voltage Transistors BiCMOS Protection RF Designs General
I/O Protection Schemes Design/layout Errors Summary 8 Failure Modes,
Reliability Issues, and Case Studies Introduction Failure Mode Analysis
Reliability and Performance Considerations Advanced CMOS Input Protection
Optimizing the Input Protection Scheme Designs for Special Applications
Process Effects on Input Protection Design Total IC Chip Protection Power
Bus Protection Internal Chip ESD Damage Stress Dependent ESD Behavior
Failure Mode Case Studies Summary 9 Influence of Processing on ESD
Introduction High Current Behavior Cross-section of a MOS Transistor
Drain-Source Implant Effects P-Well Effects N-Well Effects Epitaxial Layers
and Substrates Gate Oxides Silicides Contacts Interconnect and
Metallization Gate Length Dependencies Silicon-On-Insulator (SOI) Bipolar
Transistors Diodes Resistors Reliability Trade-Offs Summary 10 Device
Modeling of High Current Effects Introduction The Physics of ESD Damage
Thermal ("Second") Breakdown Analytical Models Using the Heat Equation
Electrothermal Device Simulations Conclusions Circuit Simulation Basics,
Approaches, and Simulations Introduction Modeling the MOSFET Modeling
Bipolar Junction Transistors Modeling Diffusion Resistors Modeling
Protection Diodes Simulation of Protection Circuits Electrothermal Circuit
Simulations Conclusion 12 Conclusions Long-term Relevance of ESD in ICs
State-of-the-art for ESD Protection Current Limitations Future Issues
Outline of the Book 2. ESD Phenomenon Introduction Electrostatic Voltage
Discharge ESD Stress Models 3. Test Methods Introduction Human Body Model
(HBM) Machine Model (MM) Charged Device Model (CDM) Socket Device Model
(SDM) Metrology, Calibration, Verification Transmission Line Pulsing (TLP)
Failure Criteria Summary 4 Physics and Operation of ESD Protection Circuits
Introduction Resistors Diodes Transistor Operation Transistor Operation
Under ESD Conditions Electrothermal Effects SCR Operation Conclusion 5 ESD
Protection Design Concepts and Strategy The Qualities of Good ESD
Protection ESD Protection Design Methods Selecting an ESD Strategy Summary
6 Design and Layout Requirements Introduction Thick Field Device NMOS
Transistors (FPDs) Gate-Coupled NMOS (GCNMOS) Gate Driven nMOS (GDNMOS) SCR
Protection Device ESD Protection Design Synthesis Total Input Protection
ESD Protection Using Diode-Based Devices Power Supply Clamps BiPolar and
BiCMOS Protection Circuits Summary 7 Advanced Protection Design
Introduction PNP Driven NMOS (PDNMOS) Substrate Triggered NMOS (STNMOS)
NMOS Triggered NMOS (NTNMOS) ESD for Mixed Voltage I/O CDM Protection SOI
Technology High Voltage Transistors BiCMOS Protection RF Designs General
I/O Protection Schemes Design/layout Errors Summary 8 Failure Modes,
Reliability Issues, and Case Studies Introduction Failure Mode Analysis
Reliability and Performance Considerations Advanced CMOS Input Protection
Optimizing the Input Protection Scheme Designs for Special Applications
Process Effects on Input Protection Design Total IC Chip Protection Power
Bus Protection Internal Chip ESD Damage Stress Dependent ESD Behavior
Failure Mode Case Studies Summary 9 Influence of Processing on ESD
Introduction High Current Behavior Cross-section of a MOS Transistor
Drain-Source Implant Effects P-Well Effects N-Well Effects Epitaxial Layers
and Substrates Gate Oxides Silicides Contacts Interconnect and
Metallization Gate Length Dependencies Silicon-On-Insulator (SOI) Bipolar
Transistors Diodes Resistors Reliability Trade-Offs Summary 10 Device
Modeling of High Current Effects Introduction The Physics of ESD Damage
Thermal ("Second") Breakdown Analytical Models Using the Heat Equation
Electrothermal Device Simulations Conclusions Circuit Simulation Basics,
Approaches, and Simulations Introduction Modeling the MOSFET Modeling
Bipolar Junction Transistors Modeling Diffusion Resistors Modeling
Protection Diodes Simulation of Protection Circuits Electrothermal Circuit
Simulations Conclusion 12 Conclusions Long-term Relevance of ESD in ICs
State-of-the-art for ESD Protection Current Limitations Future Issues
Preface 1. Introduction Background The ESD Problem Protecting against ESD
Outline of the Book 2. ESD Phenomenon Introduction Electrostatic Voltage
Discharge ESD Stress Models 3. Test Methods Introduction Human Body Model
(HBM) Machine Model (MM) Charged Device Model (CDM) Socket Device Model
(SDM) Metrology, Calibration, Verification Transmission Line Pulsing (TLP)
Failure Criteria Summary 4 Physics and Operation of ESD Protection Circuits
Introduction Resistors Diodes Transistor Operation Transistor Operation
Under ESD Conditions Electrothermal Effects SCR Operation Conclusion 5 ESD
Protection Design Concepts and Strategy The Qualities of Good ESD
Protection ESD Protection Design Methods Selecting an ESD Strategy Summary
6 Design and Layout Requirements Introduction Thick Field Device NMOS
Transistors (FPDs) Gate-Coupled NMOS (GCNMOS) Gate Driven nMOS (GDNMOS) SCR
Protection Device ESD Protection Design Synthesis Total Input Protection
ESD Protection Using Diode-Based Devices Power Supply Clamps BiPolar and
BiCMOS Protection Circuits Summary 7 Advanced Protection Design
Introduction PNP Driven NMOS (PDNMOS) Substrate Triggered NMOS (STNMOS)
NMOS Triggered NMOS (NTNMOS) ESD for Mixed Voltage I/O CDM Protection SOI
Technology High Voltage Transistors BiCMOS Protection RF Designs General
I/O Protection Schemes Design/layout Errors Summary 8 Failure Modes,
Reliability Issues, and Case Studies Introduction Failure Mode Analysis
Reliability and Performance Considerations Advanced CMOS Input Protection
Optimizing the Input Protection Scheme Designs for Special Applications
Process Effects on Input Protection Design Total IC Chip Protection Power
Bus Protection Internal Chip ESD Damage Stress Dependent ESD Behavior
Failure Mode Case Studies Summary 9 Influence of Processing on ESD
Introduction High Current Behavior Cross-section of a MOS Transistor
Drain-Source Implant Effects P-Well Effects N-Well Effects Epitaxial Layers
and Substrates Gate Oxides Silicides Contacts Interconnect and
Metallization Gate Length Dependencies Silicon-On-Insulator (SOI) Bipolar
Transistors Diodes Resistors Reliability Trade-Offs Summary 10 Device
Modeling of High Current Effects Introduction The Physics of ESD Damage
Thermal ("Second") Breakdown Analytical Models Using the Heat Equation
Electrothermal Device Simulations Conclusions Circuit Simulation Basics,
Approaches, and Simulations Introduction Modeling the MOSFET Modeling
Bipolar Junction Transistors Modeling Diffusion Resistors Modeling
Protection Diodes Simulation of Protection Circuits Electrothermal Circuit
Simulations Conclusion 12 Conclusions Long-term Relevance of ESD in ICs
State-of-the-art for ESD Protection Current Limitations Future Issues
Outline of the Book 2. ESD Phenomenon Introduction Electrostatic Voltage
Discharge ESD Stress Models 3. Test Methods Introduction Human Body Model
(HBM) Machine Model (MM) Charged Device Model (CDM) Socket Device Model
(SDM) Metrology, Calibration, Verification Transmission Line Pulsing (TLP)
Failure Criteria Summary 4 Physics and Operation of ESD Protection Circuits
Introduction Resistors Diodes Transistor Operation Transistor Operation
Under ESD Conditions Electrothermal Effects SCR Operation Conclusion 5 ESD
Protection Design Concepts and Strategy The Qualities of Good ESD
Protection ESD Protection Design Methods Selecting an ESD Strategy Summary
6 Design and Layout Requirements Introduction Thick Field Device NMOS
Transistors (FPDs) Gate-Coupled NMOS (GCNMOS) Gate Driven nMOS (GDNMOS) SCR
Protection Device ESD Protection Design Synthesis Total Input Protection
ESD Protection Using Diode-Based Devices Power Supply Clamps BiPolar and
BiCMOS Protection Circuits Summary 7 Advanced Protection Design
Introduction PNP Driven NMOS (PDNMOS) Substrate Triggered NMOS (STNMOS)
NMOS Triggered NMOS (NTNMOS) ESD for Mixed Voltage I/O CDM Protection SOI
Technology High Voltage Transistors BiCMOS Protection RF Designs General
I/O Protection Schemes Design/layout Errors Summary 8 Failure Modes,
Reliability Issues, and Case Studies Introduction Failure Mode Analysis
Reliability and Performance Considerations Advanced CMOS Input Protection
Optimizing the Input Protection Scheme Designs for Special Applications
Process Effects on Input Protection Design Total IC Chip Protection Power
Bus Protection Internal Chip ESD Damage Stress Dependent ESD Behavior
Failure Mode Case Studies Summary 9 Influence of Processing on ESD
Introduction High Current Behavior Cross-section of a MOS Transistor
Drain-Source Implant Effects P-Well Effects N-Well Effects Epitaxial Layers
and Substrates Gate Oxides Silicides Contacts Interconnect and
Metallization Gate Length Dependencies Silicon-On-Insulator (SOI) Bipolar
Transistors Diodes Resistors Reliability Trade-Offs Summary 10 Device
Modeling of High Current Effects Introduction The Physics of ESD Damage
Thermal ("Second") Breakdown Analytical Models Using the Heat Equation
Electrothermal Device Simulations Conclusions Circuit Simulation Basics,
Approaches, and Simulations Introduction Modeling the MOSFET Modeling
Bipolar Junction Transistors Modeling Diffusion Resistors Modeling
Protection Diodes Simulation of Protection Circuits Electrothermal Circuit
Simulations Conclusion 12 Conclusions Long-term Relevance of ESD in ICs
State-of-the-art for ESD Protection Current Limitations Future Issues