INVESTIGATION ON IMPROVEMENT OF QUALITY AND SECURITY ISSUES IN WIRELESS NETWORK USING VLSI

This book offers novel ideas for the advancement of fault tolerant adaptive routing algorithms for on chip interconnection networks and delineates a procedure to sense of balance the traffic load uniformly at each node in the network to enhance the performance. It is aimed in developing of efficient routing algorithms and enumerating the options of System of Buffer less structures in blockage prevention by considering understanding changes of router construction and by improving the routing methods and typologies.