ASIC Design and Synthesis RTL Design Using Verilog

Chapter 1. Introduction.- Chapter 2. Design using CMOS.- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL).- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL).- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL).- Chapter 6. ASIC design guidelines.- Chapter 7. ASIC RTL Verification.- Chapter 8. FSM using VHDL and synthesis.- Chapter 9. ASIC design improvement techniques.- Chapter 10. ASIC Synthesis using Synopsys DC.- Chapter 11. Design for Testability.- Chapter 12. Static timing analysis.- Chapter 13. Multiple Clock domain designs.- Chapter 14. Low power ASIC design.- Chapter 15. ASIC Physical design.