Multicore Systems On-Chip: Practical Software/Hardware Design
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- Hardcover
- Taschenbuch ausgewählt
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Sprache:Englisch
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Beschreibung
Produktdetails
Einband
Taschenbuch
Erscheinungsdatum
08.08.2015
Abbildungen
XXVI, 196 illus., 79 illus. in color., schwarz-weiss Illustrationen, farbige Illustrationen
Verlag
Atlantis PressSeitenzahl
273
Maße (L/B/H)
23,5/15,5/1,7 cm
Gewicht
462 g
Auflage
2013
Sprache
Englisch
ISBN
978-94-6239-050-8
The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowing to reduce the voltage on each core. Because dynamic power is proportional to the frequency and to the square of the voltage, we get a big gain, even though we may have more cores running.
As more and more cores are integrated into these designs to share the ever increasing processing load, the main challenges lie in efficient memory hierarchy, scalable system interconnect, new programming paradigms, and efficient integration methodology for connecting such heterogeneous cores into a single system capable of leveraging their individual flexibility.
Current design methods tend toward mixed HW/SW co-designs targeting multicore systems on-chip for specific applications. To decide on the lowest cost mix of cores, designers must iteratively map the device’s functionality to a particular HW/SW partition and target architectures. In addition, to connect the heterogeneous cores, the architecture requires high performance complex communication architectures and efficient communication protocols, such as hierarchical bus, point-to-point connection, or Network-on-Chip.
Software development also becomes far more complex due to the difficulties in breaking a single processing task into multiple parts that can be processed separately and then reassembled later. This reflects the fact that certain processor jobs cannot be easily parallelized to run concurrently on multiple processingcores and that load balancing between processing cores – especially heterogeneous cores – is very difficult.
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