Networks-on-Chip From Implementations to Programming Paradigms
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Form:Einzelkauf Download
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Sprache:Englisch
49,95 €
inkl. gesetzl. MwSt.Beschreibung
Produktdetails
Format
ePUB 3
Kopierschutz
Nein
Family Sharing
Nein
Text-to-Speech
Ja
Erscheinungsdatum
04.12.2014
Verlag
Elsevier Science & Techn.Seitenzahl
382 (Printausgabe)
Sprache
Englisch
EAN
9780128011782
Networks-on-Chip: From Implementations to Programming Paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC and high-level programming paradigms.
This textbook is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture and Networks-on-Chip. It is also intended for practitioners in the industry in the area of microprocessor design, especially the many-core processor design with a network-on-chip. Graduates can learn many practical and theoretical lessons from this course, and also can be motivated to delve further into the ideas and designs proposed in this book. Industrial engineers can refer to this book to make practical tradeoffs as well. Graduates and engineers who focus on off-chip network design can also refer to this book to achieve deadlock-free routing algorithm designs.
- Provides thorough and insightful exploration of NoC design space. Description from low-level logic implementations to co-optimizations of high-level program paradigms and NoCs.
- The coherent and uniform format offers readers a clear, quick and efficient exploration of NoC design space
- Covers many novel and exciting research ideas, which encourage researchers to further delve into these topics.
- Presents both engineering and theoretical contributions. The detailed description of the router, buffer and topology implementations, comparisons and analysis are of high engineering value.
This textbook is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture and Networks-on-Chip. It is also intended for practitioners in the industry in the area of microprocessor design, especially the many-core processor design with a network-on-chip. Graduates can learn many practical and theoretical lessons from this course, and also can be motivated to delve further into the ideas and designs proposed in this book. Industrial engineers can refer to this book to make practical tradeoffs as well. Graduates and engineers who focus on off-chip network design can also refer to this book to achieve deadlock-free routing algorithm designs.
- Provides thorough and insightful exploration of NoC design space. Description from low-level logic implementations to co-optimizations of high-level program paradigms and NoCs.
- The coherent and uniform format offers readers a clear, quick and efficient exploration of NoC design space
- Covers many novel and exciting research ideas, which encourage researchers to further delve into these topics.
- Presents both engineering and theoretical contributions. The detailed description of the router, buffer and topology implementations, comparisons and analysis are of high engineering value.
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