Special Issue on High Performance Clock Distribution Networks Guest Editors’ Introduction.- Clock Skew Optimization for Peak Current Reduction.- Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.- Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.- Useful-Skew Clock Routing with Gate Sizing for Low Power Design.- Clock Distribution Methodology for PowerPCTM Microprocessors.- Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology.- Practical Bounded-Skew Clock Routing.- A Clock Methodology for High-Performance Microprocessors.- Optical Clock Distribution in Electronic Systems.- Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits.