Vor Ort
Merkzettel Warenkorb
  • Produktbild: On-Chip Inductance in High Speed Integrated Circuits
  • Produktbild: On-Chip Inductance in High Speed Integrated Circuits
- 13%

On-Chip Inductance in High Speed Integrated Circuits

13% sparen

92,99 € UVP 106,99 €

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

23.10.2012

Verlag

Springer Us

Seitenzahl

303

Maße (L/B/H)

23,5/15,5/1,8 cm

Gewicht

499 g

Auflage

Softcover reprint of the original 1st ed. 2001

Sprache

Englisch

ISBN

978-1-4613-5677-6

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

23.10.2012

Verlag

Springer Us

Seitenzahl

303

Maße (L/B/H)

23,5/15,5/1,8 cm

Gewicht

499 g

Auflage

Softcover reprint of the original 1st ed. 2001

Sprache

Englisch

ISBN

978-1-4613-5677-6

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: GPSR Kontakt

Noch keine Bewertungen vorhanden

Verfassen Sie die erste Bewertung zu diesem Artikel

Helfen Sie anderen Kundinnen und Kunden durch Ihre Meinung.

Kundinnen und Kunden meinen

Bewertungen (0)
  • Produktbild: On-Chip Inductance in High Speed Integrated Circuits
  • Produktbild: On-Chip Inductance in High Speed Integrated Circuits
  • 1 Introduction.- 2 Basic Transmission Line Theory.- 2.1 Transmission Lines.- 2.2 Approximate Models for RC Interconnect.- 2.3 Repeater Insertion in RC Lines.- 3 Evaluating The Transient Response of Linear Networks.- 3.1 Elmore Delay and Wyatt Approximation.- 3.2 Higher Order Transient Response Approximations Using Moment Matching Techniques.- 4 Misfit Current-Voltage Characteristics.- 4.1 Basic Theory of Operation of a MOSFET.- 4.2 Alpha Power Law Model for Short Channel Devices.- 5 Figures of Merit to Characterize the Importance of on-Chip Inductance in Single Lines.- 5.1 Theoretical Analysis of Inductance Effects in RLC Interconnect.- 5.2 Range of Interconnect for Significant Inductance Effects.- 5.3 Conclusions.- 6 Effects of Inductance on the Propagation Delay and Repeater Insertion Process in RLC Lines.- 6.1 Propagation Delay of a Gate Driving an RLC Load.- 6.2 Repeater Insertion for an RLCInterconnect.- 6.3 Conclusions.- 7 Equivalent Elmore Delay for RLC Trees.- 7.1 Second Order Approximation for RLC Trees.- 7.2 Signal Characterization in RLC Trees for a Step Input.- 7.3 Accuracy Characterization of the Second Order Approximation.- 7.4 Conclusions.- 8 Characterizing Inductance EFFECTS in RLC Trees.- 8.1 Effect of Damping Factor and Input Rise Time.- 8.2 Results and Examples.- 8.3 Conclusions.- 9 Repeater Insertion in Tree Structured Inductive Interconnect.- 9.1 Algorithm for Repeater Insertion in RLC Trees.- 9.2 Delay Model.- 9.3 Results and Discussion.- 9.4 Summary.- 10 Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.- 10.1 Capacitive Approximation of a Lossless Transmission Line.- 10.2 Dynamic and Short-Circuit Power.- 10.3 Conclusions.- 11 Exploiting on-Chip Inductance in High speed Clock Distribution Networks.- 11.1 Useful Inductance Effects.- 11.2 Clock Distribution Network Example.- 11.3 Summary.- 12 Accurate and Efficient Evaluation of The Transient Response in RLC Circuits: the DTT Method.- 12.1 The DTT Method.- 12.2 Complexity and Stability of the DTT Method.- 12.3 Experimental Results.- 12.4 Conclusions.- 13 on the Extraction of On-Chip Inductance.- 13.1 Characteristics of On-Chip Inductance which Simplify the Extraction Process.- 13.2 Summary.- 14 Conclusions.- Appendix B — Optimum Repeater Insertion in RLC Lines.- Appendix C — Complexity of the Equivalent Elmore Delay Model.- Appendix D — Matching Conditions of A CMOS Gate Driving a Lossless Transmission Line.- Appendix E — the DTT Algorithm.- Appendix F — Comparison between DTT and Awe.- About the Authors.