Verification Techniques for System-Level Design
73,95 €
inkl. gesetzl. MwSt.Beschreibung
Produktdetails
Format
Kopierschutz
Nein
Family Sharing
Nein
Text-to-Speech
Nein
Erscheinungsdatum
27.07.2010
Verlag
Elsevier Science & Techn.Seitenzahl
256 (Printausgabe)
Sprache
Englisch
EAN
9780080553139
This book will explain how to verify SoC (Systems on Chip) logic designs using "formal and "semiformal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
- First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs
- Formal verification of high-level designs (RTL or higher)
- Verification techniques are discussed with associated system-level design methodology
- First book that covers all aspects of formal and semiformal, high-level (higher than RTL) design verification targeting SoC designs
- Formal verification of high-level designs (RTL or higher)
- Verification techniques are discussed with associated system-level design methodology
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