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Produktbild: High — Level Synthesis

High — Level Synthesis Introduction to Chip and System Design

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Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

30.09.2012

Herausgeber

Daniel D. Gajski

Verlag

Springer Us

Seitenzahl

359

Maße (L/B/H)

23,5/15,5/2,1 cm

Gewicht

569 g

Auflage

Softcover reprint of the original 1st ed. 1992

Sprache

Englisch

ISBN

978-1-4613-6617-1

Beschreibung

Rezension

`
Recommended for anyone requiring a firm foundation in the principles

of behavioural synthesis.
'

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

30.09.2012

Herausgeber

Daniel D. Gajski

Verlag

Springer Us

Seitenzahl

359

Maße (L/B/H)

23,5/15,5/2,1 cm

Gewicht

569 g

Auflage

Softcover reprint of the original 1st ed. 1992

Sprache

Englisch

ISBN

978-1-4613-6617-1

Herstelleradresse

Springer-Verlag GmbH
Tiergartenstr. 17
69121 Heidelberg
DE

Email: GPSR Kontakt

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  • Produktbild: High — Level Synthesis
  • 1 Introduction.- 1.1 The Need for Design Automation on Higher Abstraction Levels.- 1.2 Levels of Abstraction.- 1.3 Definition of Synthesis.- 1.4 Languages, Designs and Technologies.- 1.5 Essential Issues in Synthesis.- 1.6 Status and Future of High-Level Synthesis.- 1.7 Summary.- 1.8 Exercises.- 2 Architectural Models in Synthesis.- 2.1 Design Styles and Target Architectures.- 2.2 Combinatorial Logic.- 2.3 Finite State Machines.- 2.4 Finite State Machine with a Datapath.- 2.5 System Architecture.- 2.6 Engineering Considerations.- 2.7 Summary and Future Directions.- 2.8 Exercises.- 3 Quality Measures.- 3.1 Introduction.- 3.2 The Relationship between Structural and Physical Designs.- 3.3 Area Measures.- 3.4 Performance Measures.- 3.5 Other Measures.- 3.6 Summary and Future Directions.- 3.7 Exercises.- 4 Design Description Languages.- 4.1 Introduction to HDLs.- 4.2 Language Models vs. Architectural Styles.- 4.3 Programming Language Features for HDLs.- 4.4 Hardware-Specific HDL Features.- 4.5 HDL Formats.- 4.6 A Discussion of Some HDLs.- 4.7 Matching Languages to Target Architectures.- 4.8 Modeling Guidelines for HDLs.- 4.9 Summary and Future Directions.- 4.10 Exercises.- 5 Design Representation and Transformations.- 5.1 Introduction.- 5.2 Design Flow in High-Level Synthesis: An Example.- 5.3 HDL Compilation.- 5.4 Representation of HDL Behavior.- 5.5 Representation of HLS Outputs.- 5.6 Design Views and Complete Representation Schemes for High- Level Synthesis.- 5.7 Transformations.- 5.8 Summary and Future Directions.- 5.9 Exercises.- 6 Partitioning.- 6.1 Introduction.- 6.2 Basic Partitioning Methods.- 6.3 Partitioning in High-Level Synthesis.- 6.4 Summary and Future Directions.- 6.5 Exercises.- 7 Scheduling.- 7.1 Problem Definition.- 7.2 Basic Scheduling Algorithms.- 7.3 Scheduling with Relaxed Assumptions.- 7.4 Other Scheduling Formulations.- 7.5 Summary and Future Directions.- 7.6 Exercises.- 8 Allocation.- 8.1 Problem Definition.- 8.2 Datapath Architectures.- 8.3 Allocation Tasks.- 8.4 Greedy Constructive Approaches.- 8.5 Decomposition Approaches.- 8.6 Iterative Refinement Approach.- 8.7 Summary and Future Directions.- 8.8 Exercises.- 9 Design Methodology for High-Level Synthesis.- 9.1 Basic Concepts in Design Methodology.- 9.2 Generic Synthesis System.- 9.3 System Synthesis.- 9.4 Chip Synthesis.- 9.5 Logic and Sequential Synthesis.- 9.6 Physical-Design Methodology.- 9.7 System Database.- 9.8 Component Database.- 9.9 Conceptualization environment.- 9.10 Summary and Further Research.- 9.11 Exercises.