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Produktbild: Digital Integrated Circuits
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Digital Integrated Circuits

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Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

23.07.2024

Verlag

Pearson Education Limited

Seitenzahl

800

Maße (L/B/H)

23,5/17,8/4,2 cm

Gewicht

1288 g

Auflage

2

Sprache

Englisch

ISBN

978-0-13-090996-1

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

23.07.2024

Verlag

Pearson Education Limited

Seitenzahl

800

Maße (L/B/H)

23,5/17,8/4,2 cm

Gewicht

1288 g

Auflage

2

Sprache

Englisch

ISBN

978-0-13-090996-1

Herstelleradresse

Pearson
St.-Martin-Straße 82
81541 München
DE

Email: salesde@pearson.com

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  • Produktbild: Digital Integrated Circuits

  • NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.

    I. THE FABRICS
    • 1. Introduction
      • A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design.
    • 2. The Manufacturing Process
      • The CMOS Manufacturing Process. Design Rules: The Contract between Designer and Process Engineer. Packaging Integrated Circuits. Perspective: Trends in Process Technology.
    • 3. The Devices
      • The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling.
    • 4. The Wire.
      • A First Glance. Interconnect Parameters: Capitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future.
    II. A CIRCUIT PERSPECTIVE
    • 5. The CMOS Inverter
      • The Static CMOS Inverter: An Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics.
    • 6. Designing Combinational Logic Gates in CMOS
      • Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era.
    • 7. Designing Sequential Logic Circuits
      • Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy.
    III. A SYSTEM PERSPECTIVE
    • 8. Implementation Strategies for Digital ICS
      • From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. Perspective: The Implementation Platform of the Future.
    • 9. Coping with Interconnect
      • Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip.
    • 10. Timing Issues in Digital Circuits
      • Timing Classification of Digital Systems. Synchronous Design: An In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives.
    • 11. Designing Arithmetic Building Blocks
      • Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off.
    • 12. Designing Memory and Array Structures
      • The Memory Core. Memory Peripheral Circuitry. Memory Reliability and Yield. Power Dissipation in Memories. Case Studies in Memory Design. Perspective: Semiconductor Memory Trends and Evolutions.
    • Problem Solutions
    • Index