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Memory Architecture Exploration for Programmable Embedded Systems

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Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

31.12.2002

Verlag

Springer Us

Seitenzahl

128

Maße (L/B/H)

24,1/16/1,3 cm

Gewicht

880 g

Auflage

2002

Sprache

Englisch

ISBN

978-1-4020-7324-3

Beschreibung

Rezension

From the reviews:



"This book considers the opportunities and discusses the challenges in designing embedded memory system … . The book is well organized, up-to-date and easy to follow for self-study. … In general the book has high educational value. … The book is really interesting both for specialists in the topic, and graduate students … . The reviewer rates this book highly and recommends it to graduate students, researchers and practicing engineers in embedded systems design. Overall, the authors have done a commendable job … ." (Mile Stojcev, Microelectronics Reliability, Vol. 47, 2004)

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

31.12.2002

Verlag

Springer Us

Seitenzahl

128

Maße (L/B/H)

24,1/16/1,3 cm

Gewicht

880 g

Auflage

2002

Sprache

Englisch

ISBN

978-1-4020-7324-3

Herstelleradresse

Springer-Verlag KG
Sachsenplatz 4-6
1201 Wien
AT

Email: GPSR Kontakt

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  • Produktbild: Memory Architecture Exploration for Programmable Embedded Systems
  • Produktbild: Memory Architecture Exploration for Programmable Embedded Systems
  • List of Figures. List of Tables. Preface. Acknowledgements. 1: Introduction. 1.1. Motivation. 1.2. Memory Architecture Exploration for Embedded Systems. 1.3. Book Organization. 2: Related Work. 2.1.High-Level Synthesis. 2.2. Cache Optimizations. 2.3. Computer Architecture. 2.4. Disk File Systems. 2.5. Heterogeneous Memory Architectures. 2.6. Summary. 3. Early Memory Size Estimation. 3.1. Motivation. 3.2. Memory Estimation Problem. 3.3. Memory Size Estimation Algorithm. 3.4. Discussion on Parallelism vs. Memory Size. 3.5. Experiments. 3.6. Related Work. 3.7. Summary. 4: Early Memory and Connectivity Architecture Exploration. 4.1 Motivation. 4.2. Access Pattern Based Memory Architecture Exploration. 4.3. Connectivity Architecture Exploration. 4.4. Discussion on Memory Architecture. 4.5. Summary and Status. 5: Memory-Aware Compilation. 5.1. Motivation. 5.2. Memory Timing Extraction for Efficient Access Modes.5.3. Memory Miss Traffic Management. 5.4. Summary. 6: Experiments. 6.1. Experimental Setup. 6.2. Results. 6.3. Summary of Experiments. 7: Conclusions. 7.1. Summary of Contributions. 7.2. Future Directions. Bibliography. References. Index.