Power Integrity for I/O Interfaces (eBook, PDF)

With Signal Integrity/ Power Integrity Co-Design, Portable Documents

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Foreword by Joungho Kim

The Hands-On Guide to Power Integrity in Advanced Applications, from Three Industry Experts

In this book, three industry experts introduce state-of-the-art power integrity design techniques for today's most advanced digital systems, with real-life, system-level examples. They introduce a powerful approach to unifying power and signal integrity design that can identify signal impediments earlier, reducing cost and improving reliability.

After introducing high-speed, single-ended and differential I/O interfaces, the authors describe on-chip, package, and PCB power distribution networks (PDNs) and signal networks, carefully reviewing their interactions. Next, they walk through end-to-end PDN and signal network design in frequency domain, addressing crucial parameters such as self and transfer impedance. They thoroughly address modeling and characterization of on-chip components of PDNs and signal networks, evaluation of power-to-signal coupling coefficients, analysis of Simultaneous Switching Output (SSO) noise, and many other topics.

Coverage includes

The exponentially growing challenge of I/O power integrity in high-speed digital systems
PDN noise analysis and its timing impact for single-ended and differential interfaces
Concurrent design and co-simulation techniques for evaluating all power integrity effects on signal integrity
Time domain gauges for designing and optimizing components and systems
Power/signal integrity interaction mechanisms, including power noise coupling onto signal trace and noise amplification through signal resonance
Performance impact due to Inter Symbol Interference (ISI), crosstalk, and SSO noise, as well as their interactions
Validation techniques, including low impedance VNA measurements, power noise measurements, and characterization of power-to-signal coupling effects

Power Integrity for I/O Interfaces will be an indispensable resource for everyone concerned with power integrity in cutting-edge digital designs, including system design and hardware engineers, signal and power integrity engineers, graduate students, and researchers.

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Vishram S. Pandit is a technical lead in the Signal/Power Integrity Engineering team at Intel Corporation. He works on developing power delivery designs for high-speed interfaces. His focus areas include high-speed system power delivery, on-chip power delivery, and Signal/ Power Integrity co-design. Prior to Intel he worked at Hughes Network Systems on Electromagnetic Interference (EMI), Electromagnetic Compatibility (EMC), power integrity, and signal integrity technologies. He has received a B.E. (Instrumentation) from College of Engineering, Pune, India, an M.S. (Electrical Engineering) from University of Utah, USA, and an Advanced Certificate for Post-Master's Study (Computer Science) from Johns Hopkins University, USA. He is a senior member of IEEE and a member of the CPMT Technical Committee on Electrical Design, Modeling and Simulation; and he serves as a technical program committee member for DesignCon. He was a recipient of the International Engineering Consortium's paper awards for DesignCon 2008 and DesignCon 2009.

Woong Hwan Ryu is currently a Signal/Power Integrity Engineering Manager at Intel Corporation. He has been responsible for pre-silicon signal integrity and power integrity analysis for high speed interfaces. He received his Ph.D. degree in Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST). Dr. Ryu holds an IEEE Senior Member status; he serves as a reviewer for several IEEE journals; and he serves as a technical program committee member and organizing committee member for DesignCon. He was a recipient of the International Engineering Consortium's paper awards for DesignCon 2006 and DesignCon 2008. Dr. Ryu has authored and co-authored more than 80 technical publications in premier journals and international conferences, and holds three issued patents and has one patent pending.

Myoung Joon Choi is a technical lead in the Signal/Power Integrity Engineering team at Intel Corporation. He works on developing methodologies for high-speed interface simulation and analysis. His focus areas include high-speed system SI-PI co-simulation, on-chip signal and power integrity, and computational analysis of entire high-speed systems. Dr. Choi has received a Ph.D. and an M.S. from University of Illinois at Urbana-Champaign, Urbana, IL, USA, and a BS from Korea University, Seoul, Korea. He has authored and co-authored many technical publications in journals and conferences.