Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing (eBook, PDF)
From Algorithm to Architecture
Versandkostenfrei!
Sofort per Download lieferbar
40,95 €
inkl. MwSt.
Weitere Ausgaben:
PAYBACK Punkte
20 °P sammeln!
This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication...
This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G.
.Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfiguration; .Describes a unique design and optimization methodology, applied to different areas and levels, including communication theory, hardware implementation, and software support; .Demonstrates design trade-offs during different development phases and enables readers to apply similar techniques to various applications.
.Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfiguration; .Describes a unique design and optimization methodology, applied to different areas and levels, including communication theory, hardware implementation, and software support; .Demonstrates design trade-offs during different development phases and enables readers to apply similar techniques to various applications.
Dieser Download kann aus rechtlichen Gründen nur mit Rechnungsadresse in A, B, BG, CY, CZ, D, DK, EW, E, FIN, F, GR, HR, H, IRL, I, LT, L, LR, M, NL, PL, P, R, S, SLO, SK ausgeliefert werden.
Andere Kunden interessierten sich für
