Architecture of Computing Systems -- ARCS 2016 (eBook, PDF)
29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings Redaktion: Hannig, Frank; Teich, Jürgen; Schröder-Preikschat, Wolfgang; Fey, Dietmar; Pionteck, Thilo; Cardoso, João M. P.
Architecture of Computing Systems -- ARCS 2016 (eBook, PDF)
29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings Redaktion: Hannig, Frank; Teich, Jürgen; Schröder-Preikschat, Wolfgang; Fey, Dietmar; Pionteck, Thilo; Cardoso, João M. P.
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This book constitutes the proceedings of the 29th International Conference on Architecture of Computing Systems, ARCS 2016, held in Nuremberg, Germany, in April 2016. The 29 full papers presented in this volume were carefully reviewed and selected from 87 submissions. They were organized in topical sections named: configurable and in-memory accelerators; network-on-chip and secure computing architectures; cache architectures and protocols; mapping of applications on heterogeneous architectures and real-time tasks on multiprocessors; all about time: timing, tracing, and performance modeling;…mehr
This book constitutes the proceedings of the 29th International Conference on Architecture of Computing Systems, ARCS 2016, held in Nuremberg, Germany, in April 2016. The 29 full papers presented in this volume were carefully reviewed and selected from 87 submissions. They were organized in topical sections named: configurable and in-memory accelerators; network-on-chip and secure computing architectures; cache architectures and protocols; mapping of applications on heterogeneous architectures and real-time tasks on multiprocessors; all about time: timing, tracing, and performance modeling; approximate and energy-efficient computing; allocation: from memories to FPGA hardware modules; organic computing systems; and reliability aspects in NoCs, caches, and GPUs.
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Inhaltsangabe
Configurable and In-Memory Accelerators.- TowardsMulticore Performance with Configurable Computing Units.- Design and Evaluationof a Processing-in-Memory Architecture for the Smart Memory Cube.- Network-on-Chipand Secure Computing Architectures.- CASCADE: Congestion Aware Switchable CycleAdaptive Detection Router.- An Alternating Transmission Scheme for DetectionRouting based Network-on-Chips.- Exzess: Hardware-based RAM Encryption againstPhysical Memory Disclosure.- Hardware-Assisted Context Management forAccelerator Virtualization: A Case Study with RSA.- Cache Architectures andProtocols Adaptive Cache Structures.- Optimization of a Linked Cache CoherenceProtocol for Scalable Manycore Coherence.- Mapping of Applications onHeterogeneous.- Architectures and Real-Time Tasks on Multiprocessors Genericalgorithmic scheme for 2D stencil applications on heterogeneous hybrid machines.-GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive LoadBalancing.- Task Variants with Different Scratchpad Memory Consumption inMulti-Task Environments.- Feedback-Based Admission Control for Hard Real-TimeTask Allocation under Dynamic Workload on Many-core Systems.- All About Time:Timing, Tracing, and Performance Modeling Data Age Diminution in the LogicalExecution Time Model.- Accurate Sample Time Reconstruction for Sensor DataSynchronization.- DiaSys: On-Chip Trace Analysis for Multi-ProcessorSystem-on-Chip.- Analysis of Intel's Haswell Microarchitecture Using The ECMModel and Microbenchmarks.- Measurement-Based Probabilistic Timing Analysis forGraphics Processor Units.- Approximate and Energy-Efficient Computing.- ReducingEnergy Consumption of Data Transfers using Runtime Data Type Conversion.-Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector.-Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode DecisionProcess Using Actor-based Modeling.- Low-Cost Hardware Infrastructure forRuntime Thread Level Energy Accounting.- Allocation: From Memories to FPGAHardware Modules Reducing NoC and Memory Contention for Manycores.- An EfficientData Structure for Dynamic Two-Dimensional Reconfiguration.- Organic ComputingSystems Runtime Clustering of Similarly Behaving Agents in Open Organic ComputingSystems.- Comparison of Dependency Measures for the Detection of Mutual Influencesin Organic Computing Systems.- Augmenting the Algorithmic Structure of XCS byMeans of Interpolation.- Reliability Aspects in NoCs, Caches, and GPUs Estimationof End-to-end Packet Error Rates for NoC Multicasts.- Protecting Code Regionson Asymmetrically Reliable Caches.- A New Simulation-based Fault InjectionApproach for the Evaluation of Transient Errors in GPGPUs.
Configurable and In-Memory Accelerators.- TowardsMulticore Performance with Configurable Computing Units.- Design and Evaluationof a Processing-in-Memory Architecture for the Smart Memory Cube.- Network-on-Chipand Secure Computing Architectures.- CASCADE: Congestion Aware Switchable CycleAdaptive Detection Router.- An Alternating Transmission Scheme for DetectionRouting based Network-on-Chips.- Exzess: Hardware-based RAM Encryption againstPhysical Memory Disclosure.- Hardware-Assisted Context Management forAccelerator Virtualization: A Case Study with RSA.- Cache Architectures andProtocols Adaptive Cache Structures.- Optimization of a Linked Cache CoherenceProtocol for Scalable Manycore Coherence.- Mapping of Applications onHeterogeneous.- Architectures and Real-Time Tasks on Multiprocessors Genericalgorithmic scheme for 2D stencil applications on heterogeneous hybrid machines.-GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive LoadBalancing.- Task Variants with Different Scratchpad Memory Consumption inMulti-Task Environments.- Feedback-Based Admission Control for Hard Real-TimeTask Allocation under Dynamic Workload on Many-core Systems.- All About Time:Timing, Tracing, and Performance Modeling Data Age Diminution in the LogicalExecution Time Model.- Accurate Sample Time Reconstruction for Sensor DataSynchronization.- DiaSys: On-Chip Trace Analysis for Multi-ProcessorSystem-on-Chip.- Analysis of Intel's Haswell Microarchitecture Using The ECMModel and Microbenchmarks.- Measurement-Based Probabilistic Timing Analysis forGraphics Processor Units.- Approximate and Energy-Efficient Computing.- ReducingEnergy Consumption of Data Transfers using Runtime Data Type Conversion.-Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector.-Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode DecisionProcess Using Actor-based Modeling.- Low-Cost Hardware Infrastructure forRuntime Thread Level Energy Accounting.- Allocation: From Memories to FPGAHardware Modules Reducing NoC and Memory Contention for Manycores.- An EfficientData Structure for Dynamic Two-Dimensional Reconfiguration.- Organic ComputingSystems Runtime Clustering of Similarly Behaving Agents in Open Organic ComputingSystems.- Comparison of Dependency Measures for the Detection of Mutual Influencesin Organic Computing Systems.- Augmenting the Algorithmic Structure of XCS byMeans of Interpolation.- Reliability Aspects in NoCs, Caches, and GPUs Estimationof End-to-end Packet Error Rates for NoC Multicasts.- Protecting Code Regionson Asymmetrically Reliable Caches.- A New Simulation-based Fault InjectionApproach for the Evaluation of Transient Errors in GPGPUs.
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