Pallab Dasgupta

eBook, PDF

A Roadmap for Formal Property Verification (eBook, PDF)

Beschreibung

Integrating formal property verification (FPV) into an existing design process raises critical questions: Have I written enough properties? Have I written a consistent set of properties? What should I do when the FPV tool runs into capacity issues? This book develops the answers to these questions and fits them into a roadmap for formal property verification - a roadmap that shows how to glue FPV technology into the traditional validation flow.

Technische Details

• Geräte: PC
• ohne Kopierschutz
• Größe: 4.51MB

Barrierefreiheit

• Text-to-Speech

Autor

The author leads the Formal Verification Group at the Indian Institute of Technology, Kharagpur (http://www.facweb.iitkgp.ernet.in/~pallab/forverif.html). He has collaborations with leading companies, including Intel, Sun Microsystems, Synopsys, Texas Instruments, National Semiconductors, General Motors, Interra Systems and Virtio Corp, on developing formal methods for design verification. The author is a senior member of IEEE.

Produktdetails

• Verlag: Springer Netherlands
• Seitenzahl: 252
• Erscheinungstermin: 19. Januar 2007
• Englisch
• ISBN-13: 9781402047589
• Artikelnr.: 37349557

Rezensionen

"This book is a "must-read" for anyone who needs a broad and deep understanding of assertion-based verification technology and methodology. It gives an in-depth overview of the logic behind, and algorithms for, reasoning about design behavior using assertions. The book also presents advanced methods for checking consistency and coverage of an assertion-based specification, for maintaining completeness of a specification as it is refined, and for leveraging assertions for automatic test generation in constrained random simulation.Detailing both established practice and recent developments, "A Roadmap for Formal Property Verification" is a valuable reference for insight into both the present and the future of assertion-based verification." (Erich Marschner, Senior Architect, Systems and Functional Verification, Cadence Design Systems, and Co-Chair, Accellera Formal Verification Technical Committee (FVTC)