Unleash the System On Chip using FPGAs and Handel C
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With the rapid advances in technology, the conventional academic and research departments of Electronics engineering, Electrical Engineering, Computer Science, Instrumentation Engineering over the globe are forced to come together and update their curriculum with few common interdisciplinary courses in order to come out with the engineers and researchers with muli-dimensional capabilities. The gr- ing perception of the 'Hardware becoming Soft' and 'Software becoming Hard' with the emergence of the FPGAs has made its impact on both the hardware and software professionals to change their mindset...
With the rapid advances in technology, the conventional academic and research departments of Electronics engineering, Electrical Engineering, Computer Science, Instrumentation Engineering over the globe are forced to come together and update their curriculum with few common interdisciplinary courses in order to come out with the engineers and researchers with muli-dimensional capabilities. The gr- ing perception of the 'Hardware becoming Soft' and 'Software becoming Hard' with the emergence of the FPGAs has made its impact on both the hardware and software professionals to change their mindset of working in narrow domains. An interdisciplinary field where 'Hardware meets the Software' for undertaking se- ingly unfeasible tasks is System on Chip (SoC) which has become the basic pl- form of modern electronic appliances. If it wasn't for SoCs, we wouldn't be driving our car with foresight of the traffic congestion before hand using GPS. Without the omnipresence of the SoCs in our every walks of life, the society is wouldn't have evidenced the rich benefits of the convergence of the technologies such as audio, video, mobile, IPTV just to name a few. The growing expectations of the consumers have placed the field of SoC design at the heart of at variance trends. On one hand there are challenges owing to design complexities with the emergence of the new processors, RTOS, software protocol stacks, buses, while the brutal forces of deep submicron effects such as crosstalk, electromigration, timing closures are challe- ing the design metrics.
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