Turbo Coding
Hardware Acceleration of an EGPRS-2 Turbo Decoder on an FPGA
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This report presents a hardware implementation of an EGPRS-2 turbo decoder based on the soft-output Viterbi algorithm (SOVA). Here techniques for optimizing the implementation has been used to establish a Finite State Machine with Datapath (FSMD) design. EGPRS-2 is the second evolution of GPRS, a standard for wireless transmission of data over the most widespread mobile communication network in the world, GSM. The SOVA based decoder is implemented in Matlab and analyzed through profiling. Here a bottleneck is found which takes up 70 % of the decoders execution time, is found. This bottleneck i...
This report presents a hardware implementation of an EGPRS-2 turbo decoder based on the soft-output Viterbi algorithm (SOVA). Here techniques for optimizing the implementation has been used to establish a Finite State Machine with Datapath (FSMD) design. EGPRS-2 is the second evolution of GPRS, a standard for wireless transmission of data over the most widespread mobile communication network in the world, GSM. The SOVA based decoder is implemented in Matlab and analyzed through profiling. Here a bottleneck is found which takes up 70 % of the decoders execution time, is found. This bottleneck is mapped to an FSMD implementation, where the datapath is determined through cost optimization techniques and a pipeline is also implemented. XILINX Virtex-5 is used as an implementation reference to estimate a decreased execution time of the hardware design. It shows that a factor 1277 improvement over the Matlab implementation can be achieved and that it is able to handle the maximum EGPRS-2 throughput speed of 2 Mbit/s.
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